[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 25/60] target/hexagon: Remove hexagon_cpu_tlb_fill
From: |
Richard Henderson |
Subject: |
[PULL 25/60] target/hexagon: Remove hexagon_cpu_tlb_fill |
Date: |
Tue, 2 Nov 2021 07:07:05 -0400 |
The fallback code in cpu_loop_exit_sigsegv is sufficient
for hexagon linux-user.
Remove the code from cpu_loop that raises SIGSEGV.
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/hexagon/cpu_loop.c | 24 +-----------------------
target/hexagon/cpu.c | 23 -----------------------
2 files changed, 1 insertion(+), 46 deletions(-)
diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c
index bee2a9e4ea..6b24cbaba9 100644
--- a/linux-user/hexagon/cpu_loop.c
+++ b/linux-user/hexagon/cpu_loop.c
@@ -28,8 +28,7 @@
void cpu_loop(CPUHexagonState *env)
{
CPUState *cs = env_cpu(env);
- int trapnr, signum, sigcode;
- target_ulong sigaddr;
+ int trapnr;
target_ulong syscallnum;
target_ulong ret;
@@ -39,10 +38,6 @@ void cpu_loop(CPUHexagonState *env)
cpu_exec_end(cs);
process_queued_cpu_work(cs);
- signum = 0;
- sigcode = 0;
- sigaddr = 0;
-
switch (trapnr) {
case EXCP_INTERRUPT:
/* just indicate that signals should be handled asap */
@@ -65,12 +60,6 @@ void cpu_loop(CPUHexagonState *env)
env->gpr[0] = ret;
}
break;
- case HEX_EXCP_FETCH_NO_UPAGE:
- case HEX_EXCP_PRIV_NO_UREAD:
- case HEX_EXCP_PRIV_NO_UWRITE:
- signum = TARGET_SIGSEGV;
- sigcode = TARGET_SEGV_MAPERR;
- break;
case EXCP_ATOMIC:
cpu_exec_step_atomic(cs);
break;
@@ -79,17 +68,6 @@ void cpu_loop(CPUHexagonState *env)
trapnr);
exit(EXIT_FAILURE);
}
-
- if (signum) {
- target_siginfo_t info = {
- .si_signo = signum,
- .si_errno = 0,
- .si_code = sigcode,
- ._sifields._sigfault._addr = sigaddr
- };
- queue_signal(env, info.si_signo, QEMU_SI_KILL, &info);
- }
-
process_pending_signals(env);
}
}
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 3338365c16..160a46a3d5 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -245,34 +245,11 @@ static void hexagon_cpu_init(Object *obj)
qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property);
}
-static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr)
-{
-#ifdef CONFIG_USER_ONLY
- switch (access_type) {
- case MMU_INST_FETCH:
- cs->exception_index = HEX_EXCP_FETCH_NO_UPAGE;
- break;
- case MMU_DATA_LOAD:
- cs->exception_index = HEX_EXCP_PRIV_NO_UREAD;
- break;
- case MMU_DATA_STORE:
- cs->exception_index = HEX_EXCP_PRIV_NO_UWRITE;
- break;
- }
- cpu_loop_exit_restore(cs, retaddr);
-#else
-#error System mode not implemented for Hexagon
-#endif
-}
-
#include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps hexagon_tcg_ops = {
.initialize = hexagon_translate_init,
.synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
- .tlb_fill = hexagon_tlb_fill,
};
static void hexagon_cpu_class_init(ObjectClass *c, void *data)
--
2.25.1
- [PULL 01/60] accel/tcg: Split out adjust_signal_pc, (continued)
- [PULL 01/60] accel/tcg: Split out adjust_signal_pc, Richard Henderson, 2021/11/02
- [PULL 04/60] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller, Richard Henderson, 2021/11/02
- [PULL 02/60] accel/tcg: Move clear_helper_retaddr to cpu loop, Richard Henderson, 2021/11/02
- [PULL 03/60] accel/tcg: Split out handle_sigsegv_accerr_write, Richard Henderson, 2021/11/02
- [PULL 06/60] linux-user: Reorg handling for SIGSEGV, Richard Henderson, 2021/11/02
- [PULL 12/60] linux-user/host/aarch64: Populate host_signal.h, Richard Henderson, 2021/11/02
- [PULL 08/60] linux-user/host/ppc: Populate host_signal.h, Richard Henderson, 2021/11/02
- [PULL 17/60] linux-user/host/riscv: Improve host_signal_write, Richard Henderson, 2021/11/02
- [PULL 21/60] target/alpha: Implement alpha_cpu_record_sigsegv, Richard Henderson, 2021/11/02
- [PULL 19/60] hw/core: Add TCGCPUOps.record_sigsegv, Richard Henderson, 2021/11/02
- [PULL 25/60] target/hexagon: Remove hexagon_cpu_tlb_fill,
Richard Henderson <=
- [PULL 30/60] target/mips: Make mips_cpu_tlb_fill sysemu only, Richard Henderson, 2021/11/02
- [PULL 05/60] configure: Merge riscv32 and riscv64 host architectures, Richard Henderson, 2021/11/02
- [PULL 15/60] linux-user/host/riscv: Populate host_signal.h, Richard Henderson, 2021/11/02
- [PULL 28/60] target/m68k: Make m68k_cpu_tlb_fill sysemu only, Richard Henderson, 2021/11/02
- [PULL 32/60] linux-user/openrisc: Abort for EXCP_RANGE, EXCP_FPE, Richard Henderson, 2021/11/02
- [PULL 24/60] target/cris: Make cris_cpu_tlb_fill sysemu only, Richard Henderson, 2021/11/02
- [PULL 23/60] target/arm: Implement arm_cpu_record_sigsegv, Richard Henderson, 2021/11/02
- [PULL 35/60] target/riscv: Make riscv_cpu_tlb_fill sysemu only, Richard Henderson, 2021/11/02
- [PULL 31/60] target/nios2: Implement nios2_cpu_record_sigsegv, Richard Henderson, 2021/11/02
- [PULL 10/60] linux-user/host/sparc: Populate host_signal.h, Richard Henderson, 2021/11/02