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[PULL 43/44] tcg/arm: More use of the ARMInsn enum
From: |
Richard Henderson |
Subject: |
[PULL 43/44] tcg/arm: More use of the ARMInsn enum |
Date: |
Mon, 13 Sep 2021 17:14:55 -0700 |
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.c.inc | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index c068e707e8..cf0627448b 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -570,7 +570,7 @@ static void tcg_out_blx_imm(TCGContext *s, int32_t offset)
(((offset - 8) >> 2) & 0x00ffffff));
}
-static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, int opc, int rd,
+static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, int rd,
int rn, int rm, int shift)
{
tcg_out32(s, (cond << 28) | (0 << 25) | opc |
@@ -603,14 +603,14 @@ static void tcg_out_b_reg(TCGContext *s, ARMCond cond,
TCGReg rn)
}
}
-static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, int opc,
+static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc,
int rd, int rn, int im)
{
tcg_out32(s, (cond << 28) | (1 << 25) | opc |
(rn << 16) | (rd << 12) | im);
}
-static void tcg_out_ldstm(TCGContext *s, ARMCond cond, int opc,
+static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc,
TCGReg rn, uint16_t mask)
{
tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask);
@@ -637,8 +637,8 @@ static void tcg_out_memop_8(TCGContext *s, ARMCond cond,
ARMInsn opc, TCGReg rt,
(rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf));
}
-static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg
rt,
- TCGReg rn, int imm12, bool p, bool w)
+static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc,
+ TCGReg rt, TCGReg rn, int imm12, bool p, bool w)
{
bool u = 1;
if (imm12 < 0) {
@@ -873,7 +873,7 @@ static void tcg_out_movi32(TCGContext *s, ARMCond cond, int
rd, uint32_t arg)
* Emit either the reg,imm or reg,reg form of a data-processing insn.
* rhs must satisfy the "rI" constraint.
*/
-static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, int opc, TCGArg dst,
+static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, TCGArg
dst,
TCGArg lhs, TCGArg rhs, int rhs_is_const)
{
if (rhs_is_const) {
@@ -887,8 +887,8 @@ static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, int
opc, TCGArg dst,
* Emit either the reg,imm or reg,reg form of a data-processing insn.
* rhs must satisfy the "rIK" constraint.
*/
-static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, int opc, int opinv,
- TCGReg dst, TCGReg lhs, TCGArg rhs,
+static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, ARMInsn opc,
+ ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs,
bool rhs_is_const)
{
if (rhs_is_const) {
@@ -903,8 +903,8 @@ static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond,
int opc, int opinv,
}
}
-static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, int opc, int opneg,
- TCGArg dst, TCGArg lhs, TCGArg rhs,
+static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc,
+ ARMInsn opneg, TCGArg dst, TCGArg lhs, TCGArg rhs,
bool rhs_is_const)
{
/* Emit either the reg,imm or reg,reg form of a data-processing insn.
--
2.25.1
- [PULL 35/44] tcg/arm: Remove fallback definition of __ARM_ARCH, (continued)
- [PULL 35/44] tcg/arm: Remove fallback definition of __ARM_ARCH, Richard Henderson, 2021/09/13
- [PULL 38/44] tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call, Richard Henderson, 2021/09/13
- [PULL 31/44] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu, Richard Henderson, 2021/09/13
- [PULL 34/44] accel/tcg/user-exec: Fix read-modify-write of code on s390 hosts, Richard Henderson, 2021/09/13
- [PULL 29/44] target/rx: Restrict cpu_exec_interrupt() handler to sysemu, Richard Henderson, 2021/09/13
- [PULL 37/44] tcg/arm: Simplify use_armv5t_instructions, Richard Henderson, 2021/09/13
- [PULL 39/44] tcg/arm: Split out tcg_out_ldstm, Richard Henderson, 2021/09/13
- [PULL 36/44] tcg/arm: Standardize on tcg_out_<branch>_{reg,imm}, Richard Henderson, 2021/09/13
- [PULL 41/44] tcg/arm: Drop inline markers, Richard Henderson, 2021/09/13
- [PULL 43/44] tcg/arm: More use of the ARMInsn enum,
Richard Henderson <=
- [PULL 40/44] tcg/arm: Simplify usage of encode_imm, Richard Henderson, 2021/09/13
- [PULL 44/44] tcg/arm: More use of the TCGReg enum, Richard Henderson, 2021/09/13
- [PULL 42/44] tcg/arm: Give enum arm_cond_code_e a typedef and use it, Richard Henderson, 2021/09/13
- Re: [PULL 00/44] tcg patch queue, v2, Peter Maydell, 2021/09/14