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[PATCH v10 11/16] target/riscv: Add orc.b instruction for Zbb, removing
From: |
Philipp Tomsich |
Subject: |
[PATCH v10 11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci |
Date: |
Sat, 4 Sep 2021 22:35:10 +0200 |
The 1.0.0 version of Zbb does not contain gorc/gorci. Instead, a
orc.b instruction (equivalent to the orc.b pseudo-instruction built on
gorci from pre-0.93 draft-B) is available, mainly targeting
string-processing workloads.
This commit adds the new orc.b instruction and removed gorc/gorci.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v9)
Changes in v9:
- Picked up Alistair's Reviewed-by, after patman had failed to catch
it for v8.
Changes in v8:
- Optimize orc.b further by reordering the shift/and, updating the
comment to reflect that we put the truth-value into the LSB, and
putting the (now only) constant in a temporary
- Fold the final bitwise-not into the second and, using and andc.
Changes in v7:
- Free TCG temporary in gen_orc_b().
Changes in v6:
- Fixed orc.b (now passes SPEC w/ optimized string functions) by
adding the missing final negation.
Changes in v4:
- Change orc.b to implementation suggested by Richard Henderson
Changes in v3:
- Moved orc.b and gorc/gorci changes into separate commit.
- Using the simpler orc.b implementation suggested by Richard Henderson
target/riscv/bitmanip_helper.c | 26 -----------------
target/riscv/helper.h | 2 --
target/riscv/insn32.decode | 6 +---
target/riscv/insn_trans/trans_rvb.c.inc | 39 +++++++++++--------------
4 files changed, 18 insertions(+), 55 deletions(-)
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index 73be5a81c7..bb48388fcd 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -64,32 +64,6 @@ target_ulong HELPER(grevw)(target_ulong rs1, target_ulong
rs2)
return do_grev(rs1, rs2, 32);
}
-static target_ulong do_gorc(target_ulong rs1,
- target_ulong rs2,
- int bits)
-{
- target_ulong x = rs1;
- int i, shift;
-
- for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
- if (rs2 & shift) {
- x |= do_swap(x, adjacent_masks[i], shift);
- }
- }
-
- return x;
-}
-
-target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2)
-{
- return do_gorc(rs1, rs2, TARGET_LONG_BITS);
-}
-
-target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
-{
- return do_gorc(rs1, rs2, 32);
-}
-
target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
{
target_ulong result = 0;
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 8a318a2dbc..a9bda2c8ac 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -61,8 +61,6 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
/* Bitmanip */
DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index a509cfee11..59202196dc 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -681,6 +681,7 @@ max 0000101 .......... 110 ..... 0110011 @r
maxu 0000101 .......... 111 ..... 0110011 @r
min 0000101 .......... 100 ..... 0110011 @r
minu 0000101 .......... 101 ..... 0110011 @r
+orc_b 001010 000111 ..... 101 ..... 0010011 @r2
orn 0100000 .......... 110 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
ror 0110000 .......... 101 ..... 0110011 @r
@@ -702,19 +703,14 @@ pack 0000100 .......... 100 ..... 0110011 @r
packu 0100100 .......... 100 ..... 0110011 @r
packh 0000100 .......... 111 ..... 0110011 @r
grev 0110100 .......... 101 ..... 0110011 @r
-gorc 0010100 .......... 101 ..... 0110011 @r
-
grevi 01101. ........... 101 ..... 0010011 @sh
-gorci 00101. ........... 101 ..... 0010011 @sh
# *** RV64B Standard Extension (in addition to RV32B) ***
packw 0000100 .......... 100 ..... 0111011 @r
packuw 0100100 .......... 100 ..... 0111011 @r
grevw 0110100 .......... 101 ..... 0111011 @r
-gorcw 0010100 .......... 101 ..... 0111011 @r
greviw 0110100 .......... 101 ..... 0011011 @sh5
-gorciw 0010100 .......... 101 ..... 0011011 @sh5
# *** RV32 Zbc Standard Extension ***
clmul 0000101 .......... 001 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index 9768271639..05102d54b5 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -295,16 +295,27 @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
}
-static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
+static void gen_orc_b(TCGv ret, TCGv source1)
{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
+ TCGv tmp = tcg_temp_new();
+ TCGv ones = tcg_constant_tl(dup_const(MO_8, 0x01));
+
+ /* Set lsb in each byte if the byte was zero. */
+ tcg_gen_sub_tl(tmp, source1, ones);
+ tcg_gen_andc_tl(tmp, tmp, source1);
+ tcg_gen_shri_tl(tmp, tmp, 7);
+ tcg_gen_andc_tl(tmp, ones, tmp);
+
+ /* Replicate the lsb of each byte across the byte. */
+ tcg_gen_muli_tl(ret, tmp, 0xff);
+
+ tcg_temp_free(tmp);
}
-static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
+static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a)
{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
+ REQUIRE_ZBB(ctx);
+ return gen_unary(ctx, a, EXT_ZERO, gen_orc_b);
}
#define GEN_SHADD(SHAMT) \
@@ -476,22 +487,6 @@ static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
}
-static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
-}
-
-static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
-}
-
#define GEN_SHADD_UW(SHAMT) \
static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
{ \
--
2.25.1
- [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0, Philipp Tomsich, 2021/09/04
- [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1, Philipp Tomsich, 2021/09/04
- [PATCH v10 05/16] target/riscv: Reassign instructions to the Zba-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci,
Philipp Tomsich <=
- [PATCH v10 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Philipp Tomsich, 2021/09/04
- [PATCH v10 10/16] target/riscv: Reassign instructions to the Zbb-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 09/16] target/riscv: Add instructions of the Zbc-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro, Philipp Tomsich, 2021/09/04
- [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/04