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[PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extensi
From: |
Philipp Tomsich |
Subject: |
[PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension |
Date: |
Sat, 4 Sep 2021 22:35:07 +0200 |
The following instructions are part of Zbs:
- b{set,clr,ext,inv}
- b{set,clr,ext,inv}i
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v3)
Changes in v3:
- The changes to the Zbs instructions (i.e. the REQUIRE_ZBS macro) and
its use for qualifying the Zba instructions) are moved into a
separate commit.
target/riscv/insn32.decode | 17 +++++++++--------
target/riscv/insn_trans/trans_rvb.c.inc | 25 +++++++++++++++----------
2 files changed, 24 insertions(+), 18 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e0f6e315a2..35a3563ff4 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -689,19 +689,11 @@ min 0000101 .......... 100 ..... 0110011 @r
minu 0000101 .......... 101 ..... 0110011 @r
max 0000101 .......... 110 ..... 0110011 @r
maxu 0000101 .......... 111 ..... 0110011 @r
-bset 0010100 .......... 001 ..... 0110011 @r
-bclr 0100100 .......... 001 ..... 0110011 @r
-binv 0110100 .......... 001 ..... 0110011 @r
-bext 0100100 .......... 101 ..... 0110011 @r
ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
grev 0110100 .......... 101 ..... 0110011 @r
gorc 0010100 .......... 101 ..... 0110011 @r
-bseti 00101. ........... 001 ..... 0010011 @sh
-bclri 01001. ........... 001 ..... 0010011 @sh
-binvi 01101. ........... 001 ..... 0010011 @sh
-bexti 01001. ........... 101 ..... 0010011 @sh
rori 01100. ........... 101 ..... 0010011 @sh
grevi 01101. ........... 101 ..... 0010011 @sh
gorci 00101. ........... 101 ..... 0010011 @sh
@@ -722,3 +714,12 @@ roriw 0110000 .......... 101 ..... 0011011 @sh5
greviw 0110100 .......... 101 ..... 0011011 @sh5
gorciw 0010100 .......... 101 ..... 0011011 @sh5
+# *** RV32 Zbs Standard Extension ***
+bclr 0100100 .......... 001 ..... 0110011 @r
+bclri 01001. ........... 001 ..... 0010011 @sh
+bext 0100100 .......... 101 ..... 0110011 @r
+bexti 01001. ........... 101 ..... 0010011 @sh
+binv 0110100 .......... 001 ..... 0110011 @r
+binvi 01101. ........... 001 ..... 0010011 @sh
+bset 0010100 .......... 001 ..... 0110011 @r
+bseti 00101. ........... 001 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index 9891c4912a..2c2e4bc3d7 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -1,5 +1,5 @@
/*
- * RISC-V translation routines for the RVB draft and Zba Standard Extension.
+ * RISC-V translation routines for the RVB draft Zb[as] Standard Extension.
*
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
@@ -24,11 +24,16 @@
} \
} while (0)
+#define REQUIRE_ZBS(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \
+ return false; \
+ } \
+} while (0)
+
static void gen_clz(TCGv ret, TCGv arg1)
{
tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
}
-
static bool trans_clz(DisasContext *ctx, arg_clz *a)
{
REQUIRE_EXT(ctx, RVB);
@@ -165,13 +170,13 @@ static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
static bool trans_bset(DisasContext *ctx, arg_bset *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift(ctx, a, EXT_NONE, gen_bset);
}
static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
}
@@ -187,13 +192,13 @@ static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift(ctx, a, EXT_NONE, gen_bclr);
}
static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
}
@@ -209,13 +214,13 @@ static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
static bool trans_binv(DisasContext *ctx, arg_binv *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift(ctx, a, EXT_NONE, gen_binv);
}
static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
}
@@ -227,13 +232,13 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
static bool trans_bext(DisasContext *ctx, arg_bext *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift(ctx, a, EXT_NONE, gen_bext);
}
static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
}
--
2.25.1
- [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0, Philipp Tomsich, 2021/09/04
- [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1, Philipp Tomsich, 2021/09/04
- [PATCH v10 05/16] target/riscv: Reassign instructions to the Zba-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension,
Philipp Tomsich <=
- [PATCH v10 11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Philipp Tomsich, 2021/09/04
- [PATCH v10 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Philipp Tomsich, 2021/09/04
- [PATCH v10 10/16] target/riscv: Reassign instructions to the Zbb-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 09/16] target/riscv: Add instructions of the Zbc-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro, Philipp Tomsich, 2021/09/04
- [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/04