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[PULL 13/18] ppc/xive: Export PQ get/set routines
From: |
David Gibson |
Subject: |
[PULL 13/18] ppc/xive: Export PQ get/set routines |
Date: |
Fri, 27 Aug 2021 17:09:41 +1000 |
From: Cédric Le Goater <clg@kaod.org>
These will be shared with the XIVE2 router.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210809134547.689560-8-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/spapr_xive_kvm.c | 8 ++++----
hw/intc/xive.c | 6 +++---
include/hw/ppc/xive.h | 4 ++++
3 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/hw/intc/spapr_xive_kvm.c b/hw/intc/spapr_xive_kvm.c
index c008331160..3e534b9685 100644
--- a/hw/intc/spapr_xive_kvm.c
+++ b/hw/intc/spapr_xive_kvm.c
@@ -297,7 +297,7 @@ static uint8_t xive_esb_read(XiveSource *xsrc, int srcno,
uint32_t offset)
return xive_esb_rw(xsrc, srcno, offset, 0, 0) & 0x3;
}
-static void xive_esb_trigger(XiveSource *xsrc, int srcno)
+static void kvmppc_xive_esb_trigger(XiveSource *xsrc, int srcno)
{
uint64_t *addr = xsrc->esb_mmap + xive_source_esb_page(xsrc, srcno);
@@ -322,7 +322,7 @@ uint64_t kvmppc_xive_esb_rw(XiveSource *xsrc, int srcno,
uint32_t offset,
offset == XIVE_ESB_LOAD_EOI) {
xive_esb_read(xsrc, srcno, XIVE_ESB_SET_PQ_00);
if (xsrc->status[srcno] & XIVE_STATUS_ASSERTED) {
- xive_esb_trigger(xsrc, srcno);
+ kvmppc_xive_esb_trigger(xsrc, srcno);
}
return 0;
} else {
@@ -366,7 +366,7 @@ void kvmppc_xive_source_set_irq(void *opaque, int srcno,
int val)
}
}
- xive_esb_trigger(xsrc, srcno);
+ kvmppc_xive_esb_trigger(xsrc, srcno);
}
/*
@@ -533,7 +533,7 @@ static void kvmppc_xive_change_state_handler(void *opaque,
bool running,
* generate a trigger.
*/
if (pq == XIVE_ESB_RESET && old_pq == XIVE_ESB_QUEUED) {
- xive_esb_trigger(xsrc, i);
+ kvmppc_xive_esb_trigger(xsrc, i);
}
}
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index eeb4e62ba9..5ec61ec14e 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -816,7 +816,7 @@ void xive_tctx_destroy(XiveTCTX *tctx)
* XIVE ESB helpers
*/
-static uint8_t xive_esb_set(uint8_t *pq, uint8_t value)
+uint8_t xive_esb_set(uint8_t *pq, uint8_t value)
{
uint8_t old_pq = *pq & 0x3;
@@ -826,7 +826,7 @@ static uint8_t xive_esb_set(uint8_t *pq, uint8_t value)
return old_pq;
}
-static bool xive_esb_trigger(uint8_t *pq)
+bool xive_esb_trigger(uint8_t *pq)
{
uint8_t old_pq = *pq & 0x3;
@@ -846,7 +846,7 @@ static bool xive_esb_trigger(uint8_t *pq)
}
}
-static bool xive_esb_eoi(uint8_t *pq)
+bool xive_esb_eoi(uint8_t *pq)
{
uint8_t old_pq = *pq & 0x3;
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 445eccfe6b..7e25c25bfd 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -261,6 +261,10 @@ static inline hwaddr xive_source_esb_mgmt(XiveSource
*xsrc, int srcno)
#define XIVE_ESB_QUEUED (XIVE_ESB_VAL_P | XIVE_ESB_VAL_Q)
#define XIVE_ESB_OFF XIVE_ESB_VAL_Q
+bool xive_esb_trigger(uint8_t *pq);
+bool xive_esb_eoi(uint8_t *pq);
+uint8_t xive_esb_set(uint8_t *pq, uint8_t value);
+
/*
* "magic" Event State Buffer (ESB) MMIO offsets.
*
--
2.31.1
- [PULL 00/18] ppc-for-6.2 queue 20210827, David Gibson, 2021/08/27
- [PULL 02/18] spapr_pci: Fix leak in spapr_phb_vfio_get_loc_code() with g_autofree, David Gibson, 2021/08/27
- [PULL 01/18] xive: Remove extra '0x' prefix in trace events, David Gibson, 2021/08/27
- [PULL 04/18] target/ppc: moved ppc_store_sdr1 to mmu_common.c, David Gibson, 2021/08/27
- [PULL 05/18] target/ppc: moved store_40x_sler to helper_regs.c, David Gibson, 2021/08/27
- [PULL 03/18] target/ppc: divided mmu_helper.c in 2 files, David Gibson, 2021/08/27
- [PULL 12/18] ppc/pnv: add a chip topology index for POWER10, David Gibson, 2021/08/27
- [PULL 11/18] ppc/pnv: Distribute RAM among the chips, David Gibson, 2021/08/27
- [PULL 10/18] ppc/pnv: Use a simple incrementing index for the chip-id, David Gibson, 2021/08/27
- [PULL 13/18] ppc/xive: Export PQ get/set routines,
David Gibson <=
- [PULL 09/18] ppc/pnv: powerpc_excp: Do not discard HDECR exception when entering power-saving mode, David Gibson, 2021/08/27
- [PULL 07/18] ppc: Add a POWER10 DD2 CPU, David Gibson, 2021/08/27
- [PULL 08/18] ppc/pnv: Change the POWER10 machine to support DD2 only, David Gibson, 2021/08/27
- [PULL 17/18] include/qemu/int128.h: introduce bswap128s, David Gibson, 2021/08/27
- [PULL 06/18] ppc/pnv: update skiboot to commit 820d43c0a775., David Gibson, 2021/08/27
- [PULL 14/18] ppc/xive: Export xive_presenter_notify(), David Gibson, 2021/08/27
- [PULL 15/18] include/qemu/int128.h: define struct Int128 according to the host endianness, David Gibson, 2021/08/27
- [PULL 18/18] target/ppc: fix vector registers access in gdbstub for little-endian, David Gibson, 2021/08/27
- [PULL 16/18] target/ppc: fix vextu[bhw][lr]x helpers, David Gibson, 2021/08/27
- Re: [PULL 00/18] ppc-for-6.2 queue 20210827, Peter Maydell, 2021/08/28