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[PULL 33/37] target/arm: Implement HSTR.TTEE
From: |
Peter Maydell |
Subject: |
[PULL 33/37] target/arm: Implement HSTR.TTEE |
Date: |
Thu, 26 Aug 2021 18:03:03 +0100 |
In v7, the HSTR register has a TTEE bit which allows EL0/EL1 accesses
to the Thumb2EE TEECR and TEEHBR registers to be trapped to the
hypervisor. Implement these traps.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210816180305.20137-2-peter.maydell@linaro.org
---
target/arm/cpu.h | 2 ++
target/arm/helper.c | 18 ++++++++++++++++--
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 1060825c746..0cd3206041e 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1541,6 +1541,8 @@ static inline void xpsr_write(CPUARMState *env, uint32_t
val, uint32_t mask)
#define SCR_ENSCXT (1U << 25)
#define SCR_ATA (1U << 26)
+#define HSTR_TTEE (1 << 16)
+
/* Return the current FPSCR value. */
uint32_t vfp_get_fpscr(CPUARMState *env);
void vfp_set_fpscr(CPUARMState *env, uint32_t val);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 56c520cf8e9..54ac8c54b1f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2446,20 +2446,34 @@ static void teecr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
env->teecr = value;
}
+static CPAccessResult teecr_access(CPUARMState *env, const ARMCPRegInfo *ri,
+ bool isread)
+{
+ /*
+ * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE
+ * at all, so we don't need to check whether we're v8A.
+ */
+ if (arm_current_el(env) < 2 && !arm_is_secure_below_el3(env) &&
+ (env->cp15.hstr_el2 & HSTR_TTEE)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ return CP_ACCESS_OK;
+}
+
static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
if (arm_current_el(env) == 0 && (env->teecr & 1)) {
return CP_ACCESS_TRAP;
}
- return CP_ACCESS_OK;
+ return teecr_access(env, ri, isread);
}
static const ARMCPRegInfo t2ee_cp_reginfo[] = {
{ .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
.resetvalue = 0,
- .writefn = teecr_write },
+ .writefn = teecr_write, .accessfn = teecr_access },
{ .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
.accessfn = teehbr_access, .resetvalue = 0 },
--
2.20.1
- [PULL 21/37] arch_init.h: Don't include arch_init.h unnecessarily, (continued)
- [PULL 21/37] arch_init.h: Don't include arch_init.h unnecessarily, Peter Maydell, 2021/08/26
- [PULL 24/37] softmmu/physmem.c: Remove unneeded NULL check in qemu_ram_alloc_from_fd(), Peter Maydell, 2021/08/26
- [PULL 23/37] hw/core/loader: In gunzip(), check index is in range before use, not after, Peter Maydell, 2021/08/26
- [PULL 26/37] net: Zero sockaddr_in in parse_host_port(), Peter Maydell, 2021/08/26
- [PULL 30/37] raspi: Use error_fatal for SoC realize errors, not error_abort, Peter Maydell, 2021/08/26
- [PULL 28/37] tests/qtest/ipmi-bt-test: Zero-initialize sockaddr struct, Peter Maydell, 2021/08/26
- [PULL 32/37] hw/arm/virt: Delete EL3 error checksnow provided in CPU realize, Peter Maydell, 2021/08/26
- [PULL 27/37] gdbstub: Zero-initialize sockaddr structs, Peter Maydell, 2021/08/26
- [PULL 29/37] tests/tcg/multiarch/linux-test: Zero-initialize sockaddr structs, Peter Maydell, 2021/08/26
- [PULL 25/37] softmmu/physmem.c: Check return value from realpath(), Peter Maydell, 2021/08/26
- [PULL 33/37] target/arm: Implement HSTR.TTEE,
Peter Maydell <=
- [PULL 36/37] hw/arm/xlnx-versal: Add unimplemented APU mmio, Peter Maydell, 2021/08/26
- [PULL 35/37] target/arm: Do hflags rebuild in cpsr_write(), Peter Maydell, 2021/08/26
- [PULL 31/37] target/arm: Avoid assertion trying to use KVM and multiple ASes, Peter Maydell, 2021/08/26
- [PULL 37/37] hw/arm/xlnx-zynqmp: Add unimplemented APU mmio, Peter Maydell, 2021/08/26
- [PULL 34/37] target/arm: Implement HSTR.TJDBX, Peter Maydell, 2021/08/26
- Re: [PULL 00/37] target-arm queue, Peter Maydell, 2021/08/26