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[PULL 35/37] target/arm: Do hflags rebuild in cpsr_write()
From: |
Peter Maydell |
Subject: |
[PULL 35/37] target/arm: Do hflags rebuild in cpsr_write() |
Date: |
Thu, 26 Aug 2021 18:03:05 +0100 |
Currently we rely on all the callsites of cpsr_write() to rebuild the
cached hflags if they change one of the CPSR bits which we use as a
TB flag and cache in hflags. This is a bit awkward when we want to
change the set of CPSR bits that we cache, because it means we need
to re-audit all the cpsr_write() callsites to see which flags they
are writing and whether they now need to rebuild the hflags.
Switch instead to making cpsr_write() call arm_rebuild_hflags()
itself if one of the bits being changed is a cached bit.
We don't do the rebuild for the CPSRWriteRaw write type, because that
kind of write is generally doing something special anyway. For the
CPSRWriteRaw callsites in the KVM code and inbound migration we
definitely don't want to recalculate the hflags; the callsites in
boot.c and arm-powerctl.c have to do a rebuild-hflags call themselves
anyway because of other CPU state changes they make.
This allows us to drop explicit arm_rebuild_hflags() calls in a
couple of places where the only reason we needed to call it was the
CPSR write.
This fixes a bug where we were incorrectly failing to rebuild hflags
in the code path for a gdbstub write to CPSR, which meant that you
could make QEMU assert by breaking into a running guest, altering the
CPSR to change the value of, for example, CPSR.E, and then
continuing.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210817201843.3829-1-peter.maydell@linaro.org
---
target/arm/cpu.h | 10 ++++++++--
linux-user/arm/signal.c | 2 --
target/arm/helper.c | 5 +++++
3 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 09760333ccd..6a987f65e41 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1398,11 +1398,17 @@ uint32_t cpsr_read(CPUARMState *env);
typedef enum CPSRWriteType {
CPSRWriteByInstr = 0, /* from guest MSR or CPS */
CPSRWriteExceptionReturn = 1, /* from guest exception return insn */
- CPSRWriteRaw = 2, /* trust values, do not switch reg banks */
+ CPSRWriteRaw = 2,
+ /* trust values, no reg bank switch, no hflags rebuild */
CPSRWriteByGDBStub = 3, /* from the GDB stub */
} CPSRWriteType;
-/* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/
+/*
+ * Set the CPSR. Note that some bits of mask must be all-set or all-clear.
+ * This will do an arm_rebuild_hflags() if any of the bits in @mask
+ * correspond to TB flags bits cached in the hflags, unless @write_type
+ * is CPSRWriteRaw.
+ */
void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
CPSRWriteType write_type);
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
index 32b68ee302b..1dfcfd2d57b 100644
--- a/linux-user/arm/signal.c
+++ b/linux-user/arm/signal.c
@@ -289,7 +289,6 @@ setup_return(CPUARMState *env, struct target_sigaction *ka,
env->regs[14] = retcode;
env->regs[15] = handler & (thumb ? ~1 : ~3);
cpsr_write(env, cpsr, CPSR_IT | CPSR_T | CPSR_E, CPSRWriteByInstr);
- arm_rebuild_hflags(env);
return 0;
}
@@ -547,7 +546,6 @@ restore_sigcontext(CPUARMState *env, struct
target_sigcontext *sc)
__get_user(env->regs[15], &sc->arm_pc);
__get_user(cpsr, &sc->arm_cpsr);
cpsr_write(env, cpsr, CPSR_USER | CPSR_EXEC, CPSRWriteByInstr);
- arm_rebuild_hflags(env);
err |= !valid_user_regs(env);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d2dd4aa0b80..a7ae78146d4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9246,6 +9246,8 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t
mask,
CPSRWriteType write_type)
{
uint32_t changed_daif;
+ bool rebuild_hflags = (write_type != CPSRWriteRaw) &&
+ (mask & (CPSR_M | CPSR_E | CPSR_IL));
if (mask & CPSR_NZCV) {
env->ZF = (~val) & CPSR_Z;
@@ -9365,6 +9367,9 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t
mask,
}
mask &= ~CACHED_CPSR_BITS;
env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
+ if (rebuild_hflags) {
+ arm_rebuild_hflags(env);
+ }
}
/* Sign/zero extend */
--
2.20.1
- [PULL 23/37] hw/core/loader: In gunzip(), check index is in range before use, not after, (continued)
- [PULL 23/37] hw/core/loader: In gunzip(), check index is in range before use, not after, Peter Maydell, 2021/08/26
- [PULL 26/37] net: Zero sockaddr_in in parse_host_port(), Peter Maydell, 2021/08/26
- [PULL 30/37] raspi: Use error_fatal for SoC realize errors, not error_abort, Peter Maydell, 2021/08/26
- [PULL 28/37] tests/qtest/ipmi-bt-test: Zero-initialize sockaddr struct, Peter Maydell, 2021/08/26
- [PULL 32/37] hw/arm/virt: Delete EL3 error checksnow provided in CPU realize, Peter Maydell, 2021/08/26
- [PULL 27/37] gdbstub: Zero-initialize sockaddr structs, Peter Maydell, 2021/08/26
- [PULL 29/37] tests/tcg/multiarch/linux-test: Zero-initialize sockaddr structs, Peter Maydell, 2021/08/26
- [PULL 25/37] softmmu/physmem.c: Check return value from realpath(), Peter Maydell, 2021/08/26
- [PULL 33/37] target/arm: Implement HSTR.TTEE, Peter Maydell, 2021/08/26
- [PULL 36/37] hw/arm/xlnx-versal: Add unimplemented APU mmio, Peter Maydell, 2021/08/26
- [PULL 35/37] target/arm: Do hflags rebuild in cpsr_write(),
Peter Maydell <=
- [PULL 31/37] target/arm: Avoid assertion trying to use KVM and multiple ASes, Peter Maydell, 2021/08/26
- [PULL 37/37] hw/arm/xlnx-zynqmp: Add unimplemented APU mmio, Peter Maydell, 2021/08/26
- [PULL 34/37] target/arm: Implement HSTR.TJDBX, Peter Maydell, 2021/08/26
- Re: [PULL 00/37] target-arm queue, Peter Maydell, 2021/08/26