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[PULL 03/44] target/arm: Fix MVE VSLI by 0 and VSRI by <dt>
From: |
Peter Maydell |
Subject: |
[PULL 03/44] target/arm: Fix MVE VSLI by 0 and VSRI by <dt> |
Date: |
Wed, 25 Aug 2021 11:34:53 +0100 |
In the MVE shift-and-insert insns, we special case VSLI by 0
and VSRI by <dt>. VSRI by <dt> means "don't update the destination",
which is what we've implemented. However VSLI by 0 is "set
destination to the input", so we don't want to use the same
special-casing that we do for VSRI by <dt>.
Since the generic logic gives the right answer for a shift
by 0, just use that.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/mve_helper.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index db5d6220854..f14fa914b68 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -1279,11 +1279,12 @@ DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
uint16_t mask; \
uint64_t shiftmask; \
unsigned e; \
- if (shift == 0 || shift == ESIZE * 8) { \
+ if (shift == ESIZE * 8) { \
/* \
- * Only VSLI can shift by 0; only VSRI can shift by <dt>. \
- * The generic logic would give the right answer for 0 but \
- * fails for <dt>. \
+ * Only VSRI can shift by <dt>; it should mean "don't \
+ * update the destination". The generic logic can't handle \
+ * this because it would try to shift by an out-of-range \
+ * amount, so special case it here. \
*/ \
goto done; \
} \
--
2.20.1
- [PULL 00/44] target-arm queue, Peter Maydell, 2021/08/25
- [PULL 01/44] target/arm: Note that we handle VMOVL as a special case of VSHLL, Peter Maydell, 2021/08/25
- [PULL 02/44] target/arm: Print MVE VPR in CPU dumps, Peter Maydell, 2021/08/25
- [PULL 03/44] target/arm: Fix MVE VSLI by 0 and VSRI by <dt>,
Peter Maydell <=
- [PULL 06/44] target/arm: Fix 48-bit saturating shifts, Peter Maydell, 2021/08/25
- [PULL 04/44] target/arm: Fix signed VADDV, Peter Maydell, 2021/08/25
- [PULL 09/44] target/arm: Factor out mve_eci_mask(), Peter Maydell, 2021/08/25
- [PULL 05/44] target/arm: Fix mask handling for MVE narrowing operations, Peter Maydell, 2021/08/25
- [PULL 07/44] target/arm: Fix MVE 48-bit SQRSHRL for small right shifts, Peter Maydell, 2021/08/25
- [PULL 08/44] target/arm: Fix calculation of LTP mask when LR is 0, Peter Maydell, 2021/08/25
- [PULL 10/44] target/arm: Fix VPT advance when ECI is non-zero, Peter Maydell, 2021/08/25
- [PULL 11/44] target/arm: Fix VLDRB/H/W for predicated elements, Peter Maydell, 2021/08/25
- [PULL 13/44] target/arm: Implement MVE incrementing/decrementing dup insns, Peter Maydell, 2021/08/25
- [PULL 12/44] target/arm: Implement MVE VMULL (polynomial), Peter Maydell, 2021/08/25