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[PULL 08/44] target/arm: Fix calculation of LTP mask when LR is 0
From: |
Peter Maydell |
Subject: |
[PULL 08/44] target/arm: Fix calculation of LTP mask when LR is 0 |
Date: |
Wed, 25 Aug 2021 11:34:58 +0100 |
In mve_element_mask(), we calculate a mask for tail predication which
should have a number of 1 bits based on the value of LR. However,
our MAKE_64BIT_MASK() macro has undefined behaviour when passed a
zero length. Special case this to give the all-zeroes mask we
require.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/mve_helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index 1a4b2ef8075..bc67b86e700 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -64,7 +64,8 @@ static uint16_t mve_element_mask(CPUARMState *env)
*/
int masklen = env->regs[14] << env->v7m.ltpsize;
assert(masklen <= 16);
- mask &= MAKE_64BIT_MASK(0, masklen);
+ uint16_t ltpmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0;
+ mask &= ltpmask;
}
if ((env->condexec_bits & 0xf) == 0) {
--
2.20.1
- [PULL 00/44] target-arm queue, Peter Maydell, 2021/08/25
- [PULL 01/44] target/arm: Note that we handle VMOVL as a special case of VSHLL, Peter Maydell, 2021/08/25
- [PULL 02/44] target/arm: Print MVE VPR in CPU dumps, Peter Maydell, 2021/08/25
- [PULL 03/44] target/arm: Fix MVE VSLI by 0 and VSRI by <dt>, Peter Maydell, 2021/08/25
- [PULL 06/44] target/arm: Fix 48-bit saturating shifts, Peter Maydell, 2021/08/25
- [PULL 04/44] target/arm: Fix signed VADDV, Peter Maydell, 2021/08/25
- [PULL 09/44] target/arm: Factor out mve_eci_mask(), Peter Maydell, 2021/08/25
- [PULL 05/44] target/arm: Fix mask handling for MVE narrowing operations, Peter Maydell, 2021/08/25
- [PULL 07/44] target/arm: Fix MVE 48-bit SQRSHRL for small right shifts, Peter Maydell, 2021/08/25
- [PULL 08/44] target/arm: Fix calculation of LTP mask when LR is 0,
Peter Maydell <=
- [PULL 10/44] target/arm: Fix VPT advance when ECI is non-zero, Peter Maydell, 2021/08/25
- [PULL 11/44] target/arm: Fix VLDRB/H/W for predicated elements, Peter Maydell, 2021/08/25
- [PULL 13/44] target/arm: Implement MVE incrementing/decrementing dup insns, Peter Maydell, 2021/08/25
- [PULL 12/44] target/arm: Implement MVE VMULL (polynomial), Peter Maydell, 2021/08/25
- [PULL 14/44] target/arm: Factor out gen_vpst(), Peter Maydell, 2021/08/25
- [PULL 16/44] target/arm: Implement MVE integer vector-vs-scalar comparisons, Peter Maydell, 2021/08/25
- [PULL 15/44] target/arm: Implement MVE integer vector comparisons, Peter Maydell, 2021/08/25
- [PULL 19/44] target/arm: Implement MVE shift-by-scalar, Peter Maydell, 2021/08/25
- [PULL 18/44] target/arm: Implement MVE VMLAS, Peter Maydell, 2021/08/25
- [PULL 20/44] target/arm: Move 'x' and 'a' bit definitions into vmlaldav formats, Peter Maydell, 2021/08/25