Re: [PATCH v3 03/15] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits

[Richard Henderson]

On 8/23/21 9:40 AM, Philipp Tomsich wrote:
> For RV64, the shamt field in slli.uw is 6 bits wide. While the encoding
> space currently reserves a wider shamt-field (for use is a future RV128
> ISA), setting the additional bit to 1 will not map to slli.uw for RV64
> and needs to be treated as an illegal instruction.
>
> Note that this encoding being reserved for a future RV128 does not imply
> that no other instructions for RV64-only could be added in this encoding
> space in the future.
>
> As the implementation is separate from the gen_shifti helpers, we keep
> it that way and add the check for the shamt-width here.
>
> Signed-off-by: Philipp Tomsich<philipp.tomsich@vrull.eu>
> ---
>
> Changes in v3:
> - Instead of defining a new decoding format, we treat slli.uw as if it
>    had a 7bit-wide field for shamt (the 7th bit is reserved for RV128)
>    and check for validity of the encoding in C code.
>
>   target/riscv/insn_trans/trans_rvb.c.inc | 9 +++++++++
>   1 file changed, 9 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

This would be handled by gen_shift_imm_fn if rebased upon
20210820174257.548286-1-richard.henderson@linaro.org/">https://patchew.org/QEMU/20210820174257.548286-1-richard.henderson@linaro.org/


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