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[PATCH v3 02/15] target/riscv: Reassign instructions to the Zba-extensio
From: |
Philipp Tomsich |
Subject: |
[PATCH v3 02/15] target/riscv: Reassign instructions to the Zba-extension |
Date: |
Mon, 23 Aug 2021 18:40:25 +0200 |
The following instructions are part of Zba:
- add.uw (RV64 only)
- sh[123]add (RV32 and RV64)
- sh[123]add.uw (RV64-only)
- slli.uw (RV64-only)
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
Changes in v3:
- The changes to the Zba instructions (i.e. the REQUIRE_ZBA macro
and its use for qualifying the Zba instructions) are moved into
a separate commit.
target/riscv/insn32.decode | 20 ++++++++++++--------
target/riscv/insn_trans/trans_rvb.c.inc | 17 ++++++++++++-----
2 files changed, 24 insertions(+), 13 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index f09f8d5faf..68b163b72d 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -659,6 +659,18 @@ vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111
@r_wdvm
vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+# *** RV32 Zba Standard Extension ***
+sh1add 0010000 .......... 010 ..... 0110011 @r
+sh2add 0010000 .......... 100 ..... 0110011 @r
+sh3add 0010000 .......... 110 ..... 0110011 @r
+
+# *** RV64 Zba Standard Extension (in addition to RV32 Zba) ***
+add_uw 0000100 .......... 000 ..... 0111011 @r
+sh1add_uw 0010000 .......... 010 ..... 0111011 @r
+sh2add_uw 0010000 .......... 100 ..... 0111011 @r
+sh3add_uw 0010000 .......... 110 ..... 0111011 @r
+slli_uw 00001 ............ 001 ..... 0011011 @sh
+
# *** RV32B Standard Extension ***
clz 011000 000000 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
@@ -686,9 +698,6 @@ ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
grev 0110100 .......... 101 ..... 0110011 @r
gorc 0010100 .......... 101 ..... 0110011 @r
-sh1add 0010000 .......... 010 ..... 0110011 @r
-sh2add 0010000 .......... 100 ..... 0110011 @r
-sh3add 0010000 .......... 110 ..... 0110011 @r
bseti 00101. ........... 001 ..... 0010011 @sh
bclri 01001. ........... 001 ..... 0010011 @sh
@@ -717,10 +726,6 @@ rorw 0110000 .......... 101 ..... 0111011 @r
rolw 0110000 .......... 001 ..... 0111011 @r
grevw 0110100 .......... 101 ..... 0111011 @r
gorcw 0010100 .......... 101 ..... 0111011 @r
-sh1add_uw 0010000 .......... 010 ..... 0111011 @r
-sh2add_uw 0010000 .......... 100 ..... 0111011 @r
-sh3add_uw 0010000 .......... 110 ..... 0111011 @r
-add_uw 0000100 .......... 000 ..... 0111011 @r
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
bclriw 0100100 .......... 001 ..... 0011011 @sh5
@@ -731,4 +736,3 @@ roriw 0110000 .......... 101 ..... 0011011 @sh5
greviw 0110100 .......... 101 ..... 0011011 @sh5
gorciw 0010100 .......... 101 ..... 0011011 @sh5
-slli_uw 00001. ........... 001 ..... 0011011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index 9e81f6e3de..3cdd70a2b9 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -1,8 +1,9 @@
/*
- * RISC-V translation routines for the RVB Standard Extension.
+ * RISC-V translation routines for the RVB draft and Zba Standard Extension.
*
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -17,6 +18,12 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
+#define REQUIRE_ZBA(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) { \
+ return false; \
+ } \
+} while (0)
+
static bool trans_clz(DisasContext *ctx, arg_clz *a)
{
REQUIRE_EXT(ctx, RVB);
@@ -229,7 +236,7 @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
#define GEN_TRANS_SHADD(SHAMT) \
static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
{ \
- REQUIRE_EXT(ctx, RVB); \
+ REQUIRE_ZBA(ctx); \
return gen_arith(ctx, a, gen_sh##SHAMT##add); \
}
@@ -403,7 +410,7 @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,
\
arg_sh##SHAMT##add_uw *a) \
{ \
REQUIRE_64BIT(ctx); \
- REQUIRE_EXT(ctx, RVB); \
+ REQUIRE_ZBA(ctx); \
return gen_arith(ctx, a, gen_sh##SHAMT##add_uw); \
}
@@ -414,14 +421,14 @@ GEN_TRANS_SHADD_UW(3)
static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBA(ctx);
return gen_arith(ctx, a, gen_add_uw);
}
static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBA(ctx);
TCGv source1 = tcg_temp_new();
gen_get_gpr(source1, a->rs1);
--
2.25.1
- [PATCH v3 00/15] target/riscv: Update QEmu for Zb[abcs] 1.0.0, Philipp Tomsich, 2021/08/23
- [PATCH v3 02/15] target/riscv: Reassign instructions to the Zba-extension,
Philipp Tomsich <=
- [PATCH v3 03/15] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits, Philipp Tomsich, 2021/08/23
- [PATCH v3 04/15] target/riscv: Remove the W-form instructions from Zbs, Philipp Tomsich, 2021/08/23
- [PATCH v3 05/15] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B), Philipp Tomsich, 2021/08/23
- [PATCH v3 01/15] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Philipp Tomsich, 2021/08/23
- [PATCH v3 06/15] target/riscv: Reassign instructions to the Zbs-extension, Philipp Tomsich, 2021/08/23