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[PATCH v2 10/21] target/riscv: Add DisasExtend to gen_unary
From: |
Richard Henderson |
Subject: |
[PATCH v2 10/21] target/riscv: Add DisasExtend to gen_unary |
Date: |
Tue, 17 Aug 2021 11:17:52 -1000 |
Use ctx->w for ctpopw, which is the only one that can
re-use the generic algorithm for the narrow operation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/translate.c | 14 ++++++--------
target/riscv/insn_trans/trans_rvb.c.inc | 24 +++++++++---------------
2 files changed, 15 insertions(+), 23 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8d96e70abb..178d317976 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -477,17 +477,15 @@ static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
return true;
}
-static bool gen_unary(DisasContext *ctx, arg_r2 *a,
- void(*func)(TCGv, TCGv))
+static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
+ void (*func)(TCGv, TCGv))
{
- TCGv source = tcg_temp_new();
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
- gen_get_gpr(ctx, source, a->rs1);
+ func(dest, src1);
- (*func)(source, source);
-
- gen_set_gpr(ctx, a->rd, source);
- tcg_temp_free(source);
+ gen_set_gpr(ctx, a->rd, dest);
return true;
}
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index 73f088be23..e255678fff 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -26,7 +26,7 @@ static void gen_clz(TCGv ret, TCGv arg1)
static bool trans_clz(DisasContext *ctx, arg_clz *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_unary(ctx, a, gen_clz);
+ return gen_unary(ctx, a, EXT_ZERO, gen_clz);
}
static void gen_ctz(TCGv ret, TCGv arg1)
@@ -37,13 +37,13 @@ static void gen_ctz(TCGv ret, TCGv arg1)
static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_unary(ctx, a, gen_ctz);
+ return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
}
static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_unary(ctx, a, tcg_gen_ctpop_tl);
+ return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
}
static bool trans_andn(DisasContext *ctx, arg_andn *a)
@@ -132,13 +132,13 @@ static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_unary(ctx, a, tcg_gen_ext8s_tl);
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
}
static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_unary(ctx, a, tcg_gen_ext16s_tl);
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
}
static void gen_sbop_mask(TCGv ret, TCGv shamt)
@@ -366,7 +366,6 @@ GEN_TRANS_SHADD(3)
static void gen_clzw(TCGv ret, TCGv arg1)
{
- tcg_gen_ext32u_tl(ret, arg1);
tcg_gen_clzi_tl(ret, ret, 64);
tcg_gen_subi_tl(ret, ret, 32);
}
@@ -375,7 +374,7 @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
- return gen_unary(ctx, a, gen_clzw);
+ return gen_unary(ctx, a, EXT_ZERO, gen_clzw);
}
static void gen_ctzw(TCGv ret, TCGv arg1)
@@ -388,20 +387,15 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
- return gen_unary(ctx, a, gen_ctzw);
-}
-
-static void gen_cpopw(TCGv ret, TCGv arg1)
-{
- tcg_gen_ext32u_tl(arg1, arg1);
- tcg_gen_ctpop_tl(ret, arg1);
+ return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
}
static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
- return gen_unary(ctx, a, gen_cpopw);
+ ctx->w = true;
+ return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
}
static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
--
2.25.1
- Re: [PATCH v2 06/21] target/riscv: Remove gen_arith_div*, (continued)
- [PATCH v2 07/21] target/riscv: Use gen_arith for mulh and mulhu, Richard Henderson, 2021/08/17
- [PATCH v2 08/21] target/riscv: Move gen_* helpers for RVM, Richard Henderson, 2021/08/17
- [PATCH v2 09/21] target/riscv: Move gen_* helpers for RVB, Richard Henderson, 2021/08/17
- [PATCH v2 10/21] target/riscv: Add DisasExtend to gen_unary,
Richard Henderson <=
- [PATCH v2 11/21] target/riscv: Use DisasExtend in shift operations, Richard Henderson, 2021/08/17
- [PATCH v2 12/21] target/riscv: Add gen_greviw, Richard Henderson, 2021/08/17
- [PATCH v2 13/21] target/riscv: Use get_gpr in branches, Richard Henderson, 2021/08/17
- [PATCH v2 14/21] target/riscv: Use {get, dest}_gpr for integer load/store, Richard Henderson, 2021/08/17
- [PATCH v2 16/21] target/riscv: Use {get,dest}_gpr for RVA, Richard Henderson, 2021/08/17
- [PATCH v2 15/21] target/riscv: Reorg csr instructions, Richard Henderson, 2021/08/17