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[PATCH v2 14/21] target/riscv: Use {get, dest}_gpr for integer load/stor
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From: |
Richard Henderson |
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Subject: |
[PATCH v2 14/21] target/riscv: Use {get, dest}_gpr for integer load/store |
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Date: |
Tue, 17 Aug 2021 11:17:56 -1000 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvi.c.inc | 36 +++++++++++++------------
1 file changed, 19 insertions(+), 17 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index af3e0bc0e6..f616a26c82 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -138,15 +138,17 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- gen_get_gpr(ctx, t0, a->rs1);
- tcg_gen_addi_tl(t0, t0, a->imm);
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
- gen_set_gpr(ctx, a->rd, t1);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
+ if (a->imm) {
+ TCGv temp = temp_new(ctx);
+ tcg_gen_addi_tl(temp, addr, a->imm);
+ addr = temp;
+ }
+
+ tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
+ gen_set_gpr(ctx, a->rd, dest);
return true;
}
@@ -177,19 +179,19 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
{
- TCGv t0 = tcg_temp_new();
- TCGv dat = tcg_temp_new();
- gen_get_gpr(ctx, t0, a->rs1);
- tcg_gen_addi_tl(t0, t0, a->imm);
- gen_get_gpr(ctx, dat, a->rs2);
+ TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
- tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
- tcg_temp_free(t0);
- tcg_temp_free(dat);
+ if (a->imm) {
+ TCGv temp = temp_new(ctx);
+ tcg_gen_addi_tl(temp, addr, a->imm);
+ addr = temp;
+ }
+
+ tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
return true;
}
-
static bool trans_sb(DisasContext *ctx, arg_sb *a)
{
return gen_store(ctx, a, MO_SB);
--
2.25.1
- Re: [PATCH v2 08/21] target/riscv: Move gen_* helpers for RVM, (continued)
- [PATCH v2 09/21] target/riscv: Move gen_* helpers for RVB, Richard Henderson, 2021/08/17
- [PATCH v2 10/21] target/riscv: Add DisasExtend to gen_unary, Richard Henderson, 2021/08/17
- [PATCH v2 11/21] target/riscv: Use DisasExtend in shift operations, Richard Henderson, 2021/08/17
- [PATCH v2 12/21] target/riscv: Add gen_greviw, Richard Henderson, 2021/08/17
- [PATCH v2 13/21] target/riscv: Use get_gpr in branches, Richard Henderson, 2021/08/17
- [PATCH v2 14/21] target/riscv: Use {get, dest}_gpr for integer load/store,
Richard Henderson <=
- [PATCH v2 16/21] target/riscv: Use {get,dest}_gpr for RVA, Richard Henderson, 2021/08/17
- [PATCH v2 15/21] target/riscv: Reorg csr instructions, Richard Henderson, 2021/08/17
- [PATCH v2 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw, Richard Henderson, 2021/08/17
- [PATCH v2 19/21] target/riscv: Use {get,dest}_gpr for RVD, Richard Henderson, 2021/08/17
- [PATCH v2 18/21] target/riscv: Use {get,dest}_gpr for RVF, Richard Henderson, 2021/08/17