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[PATCH for-6.2 40/43] linux-user/alpha: Remove TARGET_ALIGNED_ONLY
From: |
Richard Henderson |
Subject: |
[PATCH for-6.2 40/43] linux-user/alpha: Remove TARGET_ALIGNED_ONLY |
Date: |
Wed, 28 Jul 2021 14:46:44 -1000 |
By default, the Linux kernel fixes up unaligned accesses.
Therefore, as the kernel surrogate, qemu should as well.
No fixups are done for load-locked/store-conditional, so
mark those as MO_ALIGN.
There is a syscall to disable this, and (among other things)
deliver SIGBUS, but it is essentially unused. A survey of
open source code shows no uses of SSI_NVPAIRS except trivial
examples that show how to disable unaligned fixups.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
configs/targets/alpha-linux-user.mak | 1 -
target/alpha/translate.c | 8 ++++----
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/configs/targets/alpha-linux-user.mak
b/configs/targets/alpha-linux-user.mak
index 7e62fd796a..f7d3fb4afa 100644
--- a/configs/targets/alpha-linux-user.mak
+++ b/configs/targets/alpha-linux-user.mak
@@ -1,4 +1,3 @@
TARGET_ARCH=alpha
TARGET_SYSTBL_ABI=common
TARGET_SYSTBL=syscall.tbl
-TARGET_ALIGNED_ONLY=y
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index de6c0a8439..8c60e90114 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -293,14 +293,14 @@ static inline void gen_qemu_lds(TCGv t0, TCGv t1, int
flags)
static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags)
{
- tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LESL);
+ tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LESL | MO_ALIGN);
tcg_gen_mov_i64(cpu_lock_addr, t1);
tcg_gen_mov_i64(cpu_lock_value, t0);
}
static inline void gen_qemu_ldq_l(TCGv t0, TCGv t1, int flags)
{
- tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LEQ);
+ tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LEQ | MO_ALIGN);
tcg_gen_mov_i64(cpu_lock_addr, t1);
tcg_gen_mov_i64(cpu_lock_value, t0);
}
@@ -2840,12 +2840,12 @@ static DisasJumpType translate_one(DisasContext *ctx,
uint32_t insn)
case 0x2E:
/* STL_C */
ret = gen_store_conditional(ctx, ra, rb, disp16,
- ctx->mem_idx, MO_LESL);
+ ctx->mem_idx, MO_LESL | MO_ALIGN);
break;
case 0x2F:
/* STQ_C */
ret = gen_store_conditional(ctx, ra, rb, disp16,
- ctx->mem_idx, MO_LEQ);
+ ctx->mem_idx, MO_LEQ | MO_ALIGN);
break;
case 0x30:
/* BR */
--
2.25.1
- [PATCH for-6.2 34/43] target/mips: Use cpu_*_data_ra for msa load/store, (continued)
- [PATCH for-6.2 34/43] target/mips: Use cpu_*_data_ra for msa load/store, Richard Henderson, 2021/07/28
- [PATCH for-6.2 36/43] target/s390x: Use cpu_*_mmu instead of helper_*_mmu, Richard Henderson, 2021/07/28
- [PATCH for-6.2 38/43] target/arm: Use cpu_*_mmu instead of helper_*_mmu, Richard Henderson, 2021/07/28
- [PATCH for-6.2 39/43] tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h, Richard Henderson, 2021/07/28
- [PATCH for-6.2 35/43] target/mips: Use 8-byte memory ops for msa load/store, Richard Henderson, 2021/07/28
- [PATCH for-6.2 37/43] target/sparc: Use cpu_*_mmu instead of helper_*_mmu, Richard Henderson, 2021/07/28
- [PATCH for-6.2 40/43] linux-user/alpha: Remove TARGET_ALIGNED_ONLY,
Richard Henderson <=
- [PATCH for-6.2 41/43] tcg: Add helper_unaligned_mmu for user-only sigbus, Richard Henderson, 2021/07/28
- [PATCH for-6.2 43/43] tests/tcg/multiarch: Add sigbus.c, Richard Henderson, 2021/07/28
- [PATCH for-6.2 42/43] tcg/i386: Support raising sigbus for user-only, Richard Henderson, 2021/07/28
- Re: [PATCH for-6.2 00/43] Unaligned accesses for user-only, Philippe Mathieu-Daudé, 2021/07/29