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[PULL 11/14] target/arm: Export aarch64_sve_zcr_get_valid_len
From: |
Peter Maydell |
Subject: |
[PULL 11/14] target/arm: Export aarch64_sve_zcr_get_valid_len |
Date: |
Tue, 27 Jul 2021 11:47:58 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Rename from sve_zcr_get_valid_len and make accessible
from outside of helper.c.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210723203344.968563-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/internals.h | 10 ++++++++++
target/arm/helper.c | 4 ++--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 11a72013f51..cd2ea8a3883 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -177,6 +177,16 @@ void arm_translate_init(void);
void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
#endif /* CONFIG_TCG */
+/**
+ * aarch64_sve_zcr_get_valid_len:
+ * @cpu: cpu context
+ * @start_len: maximum len to consider
+ *
+ * Return the maximum supported sve vector length <= @start_len.
+ * Note that both @start_len and the return value are in units
+ * of ZCR_ELx.LEN, so the vector bit length is (x + 1) * 128.
+ */
+uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len);
enum arm_fprounding {
FPROUNDING_TIEEVEN,
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8c1d8dbce36..155d8bf2399 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6457,7 +6457,7 @@ int sve_exception_el(CPUARMState *env, int el)
return 0;
}
-static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
+uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
{
uint32_t end_len;
@@ -6489,7 +6489,7 @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
}
- return sve_zcr_get_valid_len(cpu, zcr_len);
+ return aarch64_sve_zcr_get_valid_len(cpu, zcr_len);
}
static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
--
2.20.1
- [PULL 00/14] target-arm queue, Peter Maydell, 2021/07/27
- [PULL 01/14] hw/arm/smmuv3: Check 31st bit to see if CD is valid, Peter Maydell, 2021/07/27
- [PULL 04/14] target/arm: Add missing 'return's after calling v7m_exception_taken(), Peter Maydell, 2021/07/27
- [PULL 03/14] target/arm: Enforce that M-profile SP low 2 bits are always zero, Peter Maydell, 2021/07/27
- [PULL 02/14] qemu-options.hx: Fix formatting of -machine memory-backend option, Peter Maydell, 2021/07/27
- [PULL 07/14] hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING, Peter Maydell, 2021/07/27
- [PULL 06/14] hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts, Peter Maydell, 2021/07/27
- [PULL 05/14] target/arm: Report M-profile alignment faults correctly to the guest, Peter Maydell, 2021/07/27
- [PULL 11/14] target/arm: Export aarch64_sve_zcr_get_valid_len,
Peter Maydell <=
- [PULL 09/14] docs: Update path that mentions deprecated.rst, Peter Maydell, 2021/07/27
- [PULL 10/14] target/arm: Correctly bound length in sve_zcr_get_valid_len, Peter Maydell, 2021/07/27
- [PULL 12/14] target/arm: Add sve-default-vector-length cpu property, Peter Maydell, 2021/07/27
- [PULL 13/14] hw/arm/nseries: Display hexadecimal value with '0x' prefix, Peter Maydell, 2021/07/27
- [PULL 08/14] hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS, Peter Maydell, 2021/07/27
- [PULL 14/14] hw: aspeed_gpio: Fix memory size, Peter Maydell, 2021/07/27
- Re: [PULL 00/14] target-arm queue, Peter Maydell, 2021/07/27