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[PULL 05/14] target/arm: Report M-profile alignment faults correctly to
From: |
Peter Maydell |
Subject: |
[PULL 05/14] target/arm: Report M-profile alignment faults correctly to the guest |
Date: |
Tue, 27 Jul 2021 11:47:52 +0100 |
For M-profile, we weren't reporting alignment faults triggered by the
generic TCG code correctly to the guest. These get passed into
arm_v7m_cpu_do_interrupt() as an EXCP_DATA_ABORT with an A-profile
style exception.fsr value of 1. We didn't check for this, and so
they fell through into the default of "assume this is an MPU fault"
and were reported to the guest as a data access violation MPU fault.
Report these alignment faults as UsageFaults which set the UNALIGNED
bit in the UFSR.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210723162146.5167-4-peter.maydell@linaro.org
---
target/arm/m_helper.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index f352346a964..20761c94877 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -2248,6 +2248,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK;
break;
case EXCP_UNALIGNED:
+ /* Unaligned faults reported by M-profile aware code */
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK;
break;
@@ -2320,6 +2321,13 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
}
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
break;
+ case 0x1: /* Alignment fault reported by generic code */
+ qemu_log_mask(CPU_LOG_INT,
+ "...really UsageFault with UFSR.UNALIGNED\n");
+ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK;
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
+ env->v7m.secure);
+ break;
default:
/*
* All other FSR values are either MPU faults or "can't happen
--
2.20.1
- [PULL 00/14] target-arm queue, Peter Maydell, 2021/07/27
- [PULL 01/14] hw/arm/smmuv3: Check 31st bit to see if CD is valid, Peter Maydell, 2021/07/27
- [PULL 04/14] target/arm: Add missing 'return's after calling v7m_exception_taken(), Peter Maydell, 2021/07/27
- [PULL 03/14] target/arm: Enforce that M-profile SP low 2 bits are always zero, Peter Maydell, 2021/07/27
- [PULL 02/14] qemu-options.hx: Fix formatting of -machine memory-backend option, Peter Maydell, 2021/07/27
- [PULL 07/14] hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING, Peter Maydell, 2021/07/27
- [PULL 06/14] hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts, Peter Maydell, 2021/07/27
- [PULL 05/14] target/arm: Report M-profile alignment faults correctly to the guest,
Peter Maydell <=
- [PULL 11/14] target/arm: Export aarch64_sve_zcr_get_valid_len, Peter Maydell, 2021/07/27
- [PULL 09/14] docs: Update path that mentions deprecated.rst, Peter Maydell, 2021/07/27
- [PULL 10/14] target/arm: Correctly bound length in sve_zcr_get_valid_len, Peter Maydell, 2021/07/27
- [PULL 12/14] target/arm: Add sve-default-vector-length cpu property, Peter Maydell, 2021/07/27
- [PULL 13/14] hw/arm/nseries: Display hexadecimal value with '0x' prefix, Peter Maydell, 2021/07/27
- [PULL 08/14] hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS, Peter Maydell, 2021/07/27
- [PULL 14/14] hw: aspeed_gpio: Fix memory size, Peter Maydell, 2021/07/27
- Re: [PULL 00/14] target-arm queue, Peter Maydell, 2021/07/27