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[PATCH v2 15/22] target/loongarch: Add floating point conversion instruc
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From: |
Song Gao |
|
Subject: |
[PATCH v2 15/22] target/loongarch: Add floating point conversion instruction translation |
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Date: |
Wed, 21 Jul 2021 17:53:11 +0800 |
This patch implement floating point conversion instruction translation.
This includes:
- FCVT.S.D, FCVT.D.S
- FFINT.{S/D}.{W/L}, FTINT.{W/L}.{S/D}
- FTINT{RM/RP/RZ/RNE}.{W/L}.{S/D}
- FRINT.{S/D}
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/fpu_helper.c | 362 ++++++++++++++++++++++++++++++++++
target/loongarch/helper.h | 29 +++
target/loongarch/insns.decode | 32 +++
target/loongarch/trans.inc.c | 449 ++++++++++++++++++++++++++++++++++++++++++
4 files changed, 872 insertions(+)
diff --git a/target/loongarch/fpu_helper.c b/target/loongarch/fpu_helper.c
index 0b6a07e..162085a 100644
--- a/target/loongarch/fpu_helper.c
+++ b/target/loongarch/fpu_helper.c
@@ -991,3 +991,365 @@ uint64_t helper_fp_cmp_sune_d(CPULoongArchState *env,
uint64_t fp,
return 0;
}
}
+
+/* floating point conversion */
+uint64_t helper_fp_cvt_d_s(CPULoongArchState *env, uint32_t src)
+{
+ uint64_t dest;
+
+ dest = float32_to_float64(src, &env->active_fpu.fp_status);
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint64_t helper_fp_fint_d_w(CPULoongArchState *env, uint32_t src)
+{
+ uint64_t dest;
+
+ dest = int32_to_float64(src, &env->active_fpu.fp_status);
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint64_t helper_fp_fint_d_l(CPULoongArchState *env, uint64_t src)
+{
+ uint64_t dest;
+
+ dest = int64_to_float64(src, &env->active_fpu.fp_status);
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint32_t helper_fp_cvt_s_d(CPULoongArchState *env, uint64_t src)
+{
+ uint32_t dest;
+
+ dest = float64_to_float32(src, &env->active_fpu.fp_status);
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint32_t helper_fp_fint_s_w(CPULoongArchState *env, uint32_t src)
+{
+ uint32_t dest;
+
+ dest = int32_to_float32(src, &env->active_fpu.fp_status);
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint32_t helper_fp_fint_s_l(CPULoongArchState *env, uint64_t src)
+{
+ uint32_t dest;
+
+ dest = int64_to_float32(src, &env->active_fpu.fp_status);
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint64_t helper_fp_tintrm_l_d(CPULoongArchState *env, uint64_t src)
+{
+ uint64_t dest;
+
+ set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
+ dest = float64_to_int64(src, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dest = FP_TO_INT64_OVERFLOW;
+ }
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint64_t helper_fp_tintrm_l_s(CPULoongArchState *env, uint32_t src)
+{
+ uint64_t dest;
+
+ set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
+ dest = float32_to_int64(src, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dest = FP_TO_INT64_OVERFLOW;
+ }
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint32_t helper_fp_tintrm_w_d(CPULoongArchState *env, uint64_t src)
+{
+ uint32_t dest;
+
+ set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
+ dest = float64_to_int32(src, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dest = FP_TO_INT32_OVERFLOW;
+ }
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint32_t helper_fp_tintrm_w_s(CPULoongArchState *env, uint32_t src)
+{
+ uint32_t dest;
+
+ set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
+ dest = float32_to_int32(src, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dest = FP_TO_INT32_OVERFLOW;
+ }
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint64_t helper_fp_tintrp_l_d(CPULoongArchState *env, uint64_t src)
+{
+ uint64_t dest;
+
+ set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
+ dest = float64_to_int64(src, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dest = FP_TO_INT64_OVERFLOW;
+ }
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint64_t helper_fp_tintrp_l_s(CPULoongArchState *env, uint32_t src)
+{
+ uint64_t dest;
+
+ set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
+ dest = float32_to_int64(src, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dest = FP_TO_INT64_OVERFLOW;
+ }
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint32_t helper_fp_tintrp_w_d(CPULoongArchState *env, uint64_t src)
+{
+ uint32_t dest;
+
+ set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
+ dest = float64_to_int32(src, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dest = FP_TO_INT32_OVERFLOW;
+ }
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint32_t helper_fp_tintrp_w_s(CPULoongArchState *env, uint32_t src)
+{
+ uint32_t dest;
+
+ set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
+ dest = float32_to_int32(src, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dest = FP_TO_INT32_OVERFLOW;
+ }
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint64_t helper_fp_tintrz_l_d(CPULoongArchState *env, uint64_t src)
+{
+ uint64_t dest;
+
+ dest = float64_to_int64_round_to_zero(src,
+ &env->active_fpu.fp_status);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dest = FP_TO_INT64_OVERFLOW;
+ }
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint64_t helper_fp_tintrz_l_s(CPULoongArchState *env, uint32_t src)
+{
+ uint64_t dest;
+
+ dest = float32_to_int64_round_to_zero(src, &env->active_fpu.fp_status);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dest = FP_TO_INT64_OVERFLOW;
+ }
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint32_t helper_fp_tintrz_w_d(CPULoongArchState *env, uint64_t src)
+{
+ uint32_t dest;
+
+ dest = float64_to_int32_round_to_zero(src, &env->active_fpu.fp_status);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dest = FP_TO_INT32_OVERFLOW;
+ }
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint32_t helper_fp_tintrz_w_s(CPULoongArchState *env, uint32_t src)
+{
+ uint32_t dest;
+
+ dest = float32_to_int32_round_to_zero(src, &env->active_fpu.fp_status);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dest = FP_TO_INT32_OVERFLOW;
+ }
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint64_t helper_fp_tintrne_l_d(CPULoongArchState *env, uint64_t src)
+{
+ uint64_t dest;
+
+ set_float_rounding_mode(float_round_nearest_even,
+ &env->active_fpu.fp_status);
+ dest = float64_to_int64(src, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dest = FP_TO_INT64_OVERFLOW;
+ }
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint64_t helper_fp_tintrne_l_s(CPULoongArchState *env, uint32_t src)
+{
+ uint64_t dest;
+
+ set_float_rounding_mode(float_round_nearest_even,
+ &env->active_fpu.fp_status);
+ dest = float32_to_int64(src, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dest = FP_TO_INT64_OVERFLOW;
+ }
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint32_t helper_fp_tintrne_w_d(CPULoongArchState *env, uint64_t src)
+{
+ uint32_t dest;
+
+ set_float_rounding_mode(float_round_nearest_even,
+ &env->active_fpu.fp_status);
+ dest = float64_to_int32(src, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dest = FP_TO_INT32_OVERFLOW;
+ }
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint32_t helper_fp_tintrne_w_s(CPULoongArchState *env, uint32_t src)
+{
+ uint32_t dest;
+
+ set_float_rounding_mode(float_round_nearest_even,
+ &env->active_fpu.fp_status);
+ dest = float32_to_int32(src, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dest = FP_TO_INT32_OVERFLOW;
+ }
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint64_t helper_fp_tint_l_d(CPULoongArchState *env, uint64_t src)
+{
+ uint64_t dest;
+
+ dest = float64_to_int64(src, &env->active_fpu.fp_status);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dest = FP_TO_INT64_OVERFLOW;
+ }
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint64_t helper_fp_tint_l_s(CPULoongArchState *env, uint32_t src)
+{
+ uint64_t dest;
+
+ dest = float32_to_int64(src, &env->active_fpu.fp_status);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dest = FP_TO_INT64_OVERFLOW;
+ }
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint32_t helper_fp_tint_w_s(CPULoongArchState *env, uint32_t src)
+{
+ uint32_t dest;
+
+ dest = float32_to_int32(src, &env->active_fpu.fp_status);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dest = FP_TO_INT32_OVERFLOW;
+ }
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint32_t helper_fp_tint_w_d(CPULoongArchState *env, uint64_t src)
+{
+ uint32_t dest;
+
+ dest = float64_to_int32(src, &env->active_fpu.fp_status);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dest = FP_TO_INT32_OVERFLOW;
+ }
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint32_t helper_fp_rint_s(CPULoongArchState *env, uint32_t src)
+{
+ uint32_t dest;
+
+ dest = float32_round_to_int(src, &env->active_fpu.fp_status);
+ update_fcsr0(env, GETPC());
+ return dest;
+}
+
+uint64_t helper_fp_rint_d(CPULoongArchState *env, uint64_t src)
+{
+ uint64_t dest;
+
+ dest = float64_round_to_int(src, &env->active_fpu.fp_status);
+ update_fcsr0(env, GETPC());
+ return dest;
+}
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index b1a81c5..9ec2b53 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -69,6 +69,8 @@ DEF_HELPER_2(fp_rsqrt_s, i32, env, i32)
DEF_HELPER_2(fp_rsqrt_d, i64, env, i64)
DEF_HELPER_2(fp_recip_s, i32, env, i32)
DEF_HELPER_2(fp_recip_d, i64, env, i64)
+DEF_HELPER_2(fp_rint_s, i32, env, i32)
+DEF_HELPER_2(fp_rint_d, i64, env, i64)
DEF_HELPER_FLAGS_2(fp_class_s, TCG_CALL_NO_RWG_SE, i32, env, i32)
DEF_HELPER_FLAGS_2(fp_class_d, TCG_CALL_NO_RWG_SE, i64, env, i64)
@@ -121,3 +123,30 @@ DEF_HELPER_3(fp_cmp_sune_s, i32, env, i32, i32)
DEF_HELPER_3(movreg2cf_i32, void, env, i32, i32)
DEF_HELPER_3(movreg2cf_i64, void, env, i32, i64)
+
+DEF_HELPER_2(fp_cvt_d_s, i64, env, i32)
+DEF_HELPER_2(fp_cvt_s_d, i32, env, i64)
+DEF_HELPER_2(fp_fint_d_w, i64, env, i32)
+DEF_HELPER_2(fp_fint_d_l, i64, env, i64)
+DEF_HELPER_2(fp_fint_s_w, i32, env, i32)
+DEF_HELPER_2(fp_fint_s_l, i32, env, i64)
+DEF_HELPER_2(fp_tintrm_l_s, i64, env, i32)
+DEF_HELPER_2(fp_tintrm_l_d, i64, env, i64)
+DEF_HELPER_2(fp_tintrm_w_s, i32, env, i32)
+DEF_HELPER_2(fp_tintrm_w_d, i32, env, i64)
+DEF_HELPER_2(fp_tintrp_l_s, i64, env, i32)
+DEF_HELPER_2(fp_tintrp_l_d, i64, env, i64)
+DEF_HELPER_2(fp_tintrp_w_s, i32, env, i32)
+DEF_HELPER_2(fp_tintrp_w_d, i32, env, i64)
+DEF_HELPER_2(fp_tintrz_l_s, i64, env, i32)
+DEF_HELPER_2(fp_tintrz_l_d, i64, env, i64)
+DEF_HELPER_2(fp_tintrz_w_s, i32, env, i32)
+DEF_HELPER_2(fp_tintrz_w_d, i32, env, i64)
+DEF_HELPER_2(fp_tintrne_l_s, i64, env, i32)
+DEF_HELPER_2(fp_tintrne_l_d, i64, env, i64)
+DEF_HELPER_2(fp_tintrne_w_s, i32, env, i32)
+DEF_HELPER_2(fp_tintrne_w_d, i32, env, i64)
+DEF_HELPER_2(fp_tint_l_s, i64, env, i32)
+DEF_HELPER_2(fp_tint_l_d, i64, env, i64)
+DEF_HELPER_2(fp_tint_w_s, i32, env, i32)
+DEF_HELPER_2(fp_tint_w_d, i32, env, i64)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 8aadcfd..c6fd762 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -351,3 +351,35 @@ fclass_d 0000 00010001 01000 01110 ..... .....
@fmt_fdfj
#
fcmp_cond_s 0000 11000001 ..... ..... ..... 00 ... @fmt_cdfjfkfcond
fcmp_cond_d 0000 11000010 ..... ..... ..... 00 ... @fmt_cdfjfkfcond
+
+#
+# Floating point conversion instruction
+#
+fcvt_s_d 0000 00010001 10010 00110 ..... ..... @fmt_fdfj
+fcvt_d_s 0000 00010001 10010 01001 ..... ..... @fmt_fdfj
+ftintrm_w_s 0000 00010001 10100 00001 ..... ..... @fmt_fdfj
+ftintrm_w_d 0000 00010001 10100 00010 ..... ..... @fmt_fdfj
+ftintrm_l_s 0000 00010001 10100 01001 ..... ..... @fmt_fdfj
+ftintrm_l_d 0000 00010001 10100 01010 ..... ..... @fmt_fdfj
+ftintrp_w_s 0000 00010001 10100 10001 ..... ..... @fmt_fdfj
+ftintrp_w_d 0000 00010001 10100 10010 ..... ..... @fmt_fdfj
+ftintrp_l_s 0000 00010001 10100 11001 ..... ..... @fmt_fdfj
+ftintrp_l_d 0000 00010001 10100 11010 ..... ..... @fmt_fdfj
+ftintrz_w_s 0000 00010001 10101 00001 ..... ..... @fmt_fdfj
+ftintrz_w_d 0000 00010001 10101 00010 ..... ..... @fmt_fdfj
+ftintrz_l_s 0000 00010001 10101 01001 ..... ..... @fmt_fdfj
+ftintrz_l_d 0000 00010001 10101 01010 ..... ..... @fmt_fdfj
+ftintrne_w_s 0000 00010001 10101 10001 ..... ..... @fmt_fdfj
+ftintrne_w_d 0000 00010001 10101 10010 ..... ..... @fmt_fdfj
+ftintrne_l_s 0000 00010001 10101 11001 ..... ..... @fmt_fdfj
+ftintrne_l_d 0000 00010001 10101 11010 ..... ..... @fmt_fdfj
+ftint_w_s 0000 00010001 10110 00001 ..... ..... @fmt_fdfj
+ftint_w_d 0000 00010001 10110 00010 ..... ..... @fmt_fdfj
+ftint_l_s 0000 00010001 10110 01001 ..... ..... @fmt_fdfj
+ftint_l_d 0000 00010001 10110 01010 ..... ..... @fmt_fdfj
+ffint_s_w 0000 00010001 11010 00100 ..... ..... @fmt_fdfj
+ffint_s_l 0000 00010001 11010 00110 ..... ..... @fmt_fdfj
+ffint_d_w 0000 00010001 11010 01000 ..... ..... @fmt_fdfj
+ffint_d_l 0000 00010001 11010 01010 ..... ..... @fmt_fdfj
+frint_s 0000 00010001 11100 10001 ..... ..... @fmt_fdfj
+frint_d 0000 00010001 11100 10010 ..... ..... @fmt_fdfj
diff --git a/target/loongarch/trans.inc.c b/target/loongarch/trans.inc.c
index a4efc05..aa9920e 100644
--- a/target/loongarch/trans.inc.c
+++ b/target/loongarch/trans.inc.c
@@ -4309,3 +4309,452 @@ static bool trans_fcmp_cond_d(DisasContext *ctx,
arg_fcmp_cond_d *a)
return true;
}
+
+/* Floating point conversion instruction */
+static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a)
+{
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr64(fp64, a->fj);
+ gen_helper_fp_cvt_s_d(fp32, cpu_env, fp64);
+ gen_store_fpr32(fp32, a->fd);
+
+ tcg_temp_free_i32(fp32);
+ tcg_temp_free_i64(fp64);
+
+ return true;
+}
+
+static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a)
+{
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr32(fp32, a->fj);
+ gen_helper_fp_cvt_d_s(fp64, cpu_env, fp32);
+ gen_store_fpr64(fp64, a->fd);
+
+ tcg_temp_free_i32(fp32);
+ tcg_temp_free_i64(fp64);
+
+ return true;
+}
+
+static bool trans_ftintrm_w_s(DisasContext *ctx, arg_ftintrm_l_s *a)
+{
+ TCGv_i32 fp0;
+
+ fp0 = tcg_temp_new_i32();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr32(fp0, a->fj);
+ gen_helper_fp_tintrm_w_s(fp0, cpu_env, fp0);
+ gen_store_fpr32(fp0, a->fd);
+
+ tcg_temp_free_i32(fp0);
+
+ return true;
+}
+
+static bool trans_ftintrm_w_d(DisasContext *ctx, arg_ftintrm_l_d *a)
+{
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr64(fp64, a->fj);
+ gen_helper_fp_tintrm_w_d(fp32, cpu_env, fp64);
+ gen_store_fpr32(fp32, a->fd);
+
+ tcg_temp_free_i32(fp32);
+ tcg_temp_free_i64(fp64);
+
+ return true;
+}
+
+static bool trans_ftintrm_l_s(DisasContext *ctx, arg_ftintrm_l_s *a)
+{
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr32(fp32, a->fj);
+ gen_helper_fp_tintrm_l_s(fp64, cpu_env, fp32);
+ gen_store_fpr64(fp64, a->fd);
+
+ tcg_temp_free_i32(fp32);
+ tcg_temp_free_i64(fp64);
+
+ return true;
+}
+
+static bool trans_ftintrm_l_d(DisasContext *ctx, arg_ftintrm_l_d *a)
+{
+ TCGv_i64 fp0;
+
+ fp0 = tcg_temp_new_i64();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr64(fp0, a->fj);
+ gen_helper_fp_tintrm_l_d(fp0, cpu_env, fp0);
+ gen_store_fpr64(fp0, a->fd);
+
+ tcg_temp_free_i64(fp0);
+
+ return true;
+}
+
+static bool trans_ftintrp_w_s(DisasContext *ctx, arg_ftintrp_w_s *a)
+{
+ TCGv_i32 fp0;
+
+ fp0 = tcg_temp_new_i32();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr32(fp0, a->fj);
+ gen_helper_fp_tintrp_w_s(fp0, cpu_env, fp0);
+ gen_store_fpr32(fp0, a->fd);
+
+ tcg_temp_free_i32(fp0);
+
+ return true;
+}
+
+static bool trans_ftintrp_w_d(DisasContext *ctx, arg_ftintrp_w_d *a)
+{
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr64(fp64, a->fj);
+ gen_helper_fp_tintrp_w_d(fp32, cpu_env, fp64);
+ gen_store_fpr32(fp32, a->fd);
+
+ tcg_temp_free_i32(fp32);
+ tcg_temp_free_i64(fp64);
+
+ return true;
+}
+
+static bool trans_ftintrp_l_s(DisasContext *ctx, arg_ftintrp_l_s *a)
+{
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr32(fp32, a->fj);
+ gen_helper_fp_tintrp_l_s(fp64, cpu_env, fp32);
+ gen_store_fpr64(fp64, a->fd);
+
+ tcg_temp_free_i32(fp32);
+ tcg_temp_free_i64(fp64);
+
+ return true;
+}
+
+static bool trans_ftintrp_l_d(DisasContext *ctx, arg_ftintrp_l_d *a)
+{
+ TCGv_i64 fp0;
+
+ fp0 = tcg_temp_new_i64();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr64(fp0, a->fj);
+ gen_helper_fp_tintrp_l_d(fp0, cpu_env, fp0);
+ gen_store_fpr64(fp0, a->fd);
+
+ tcg_temp_free_i64(fp0);
+
+ return true;
+}
+
+static bool trans_ftintrz_w_s(DisasContext *ctx, arg_ftintrz_w_s *a)
+{
+ TCGv_i32 fp0;
+
+ fp0 = tcg_temp_new_i32();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr32(fp0, a->fj);
+ gen_helper_fp_tintrz_w_s(fp0, cpu_env, fp0);
+ gen_store_fpr32(fp0, a->fd);
+
+ tcg_temp_free_i32(fp0);
+
+ return true;
+}
+
+static bool trans_ftintrz_w_d(DisasContext *ctx, arg_ftintrz_w_d *a)
+{
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr64(fp64, a->fj);
+ gen_helper_fp_tintrz_w_d(fp32, cpu_env, fp64);
+ gen_store_fpr32(fp32, a->fd);
+
+ tcg_temp_free_i32(fp32);
+ tcg_temp_free_i64(fp64);
+
+ return true;
+}
+
+static bool trans_ftintrz_l_s(DisasContext *ctx, arg_ftintrz_l_s *a)
+{
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr32(fp32, a->fj);
+ gen_helper_fp_tintrz_l_s(fp64, cpu_env, fp32);
+ gen_store_fpr64(fp64, a->fd);
+
+ tcg_temp_free_i32(fp32);
+ tcg_temp_free_i64(fp64);
+
+ return true;
+}
+
+static bool trans_ftintrz_l_d(DisasContext *ctx, arg_ftintrz_l_d *a)
+{
+ TCGv_i64 fp0;
+
+ fp0 = tcg_temp_new_i64();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr64(fp0, a->fj);
+ gen_helper_fp_tintrz_l_d(fp0, cpu_env, fp0);
+ gen_store_fpr64(fp0, a->fd);
+
+ tcg_temp_free_i64(fp0);
+
+ return true;
+}
+
+static bool trans_ftintrne_w_s(DisasContext *ctx, arg_ftintrne_w_s *a)
+{
+ TCGv_i32 fp0;
+
+ fp0 = tcg_temp_new_i32();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr32(fp0, a->fj);
+ gen_helper_fp_tintrne_w_s(fp0, cpu_env, fp0);
+ gen_store_fpr32(fp0, a->fd);
+
+ tcg_temp_free_i32(fp0);
+
+ return true;
+}
+
+static bool trans_ftintrne_w_d(DisasContext *ctx, arg_ftintrne_w_d *a)
+{
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr64(fp64, a->fj);
+ gen_helper_fp_tintrne_w_d(fp32, cpu_env, fp64);
+ gen_store_fpr32(fp32, a->fd);
+
+ tcg_temp_free_i32(fp32);
+ tcg_temp_free_i64(fp64);
+
+ return true;
+}
+
+static bool trans_ftintrne_l_s(DisasContext *ctx, arg_ftintrne_l_s *a)
+{
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr32(fp32, a->fj);
+ gen_helper_fp_tintrne_l_s(fp64, cpu_env, fp32);
+ gen_store_fpr64(fp64, a->fd);
+
+ tcg_temp_free_i32(fp32);
+ tcg_temp_free_i64(fp64);
+
+ return true;
+}
+
+static bool trans_ftintrne_l_d(DisasContext *ctx, arg_ftintrne_l_d *a)
+{
+ TCGv_i64 fp0;
+
+ fp0 = tcg_temp_new_i64();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr64(fp0, a->fj);
+ gen_helper_fp_tintrne_l_d(fp0, cpu_env, fp0);
+ gen_store_fpr64(fp0, a->fd);
+
+ tcg_temp_free_i64(fp0);
+
+ return true;
+}
+
+static bool trans_ftint_w_s(DisasContext *ctx, arg_ftint_w_s *a)
+{
+ TCGv_i32 fp0;
+
+ fp0 = tcg_temp_new_i32();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr32(fp0, a->fj);
+ gen_helper_fp_tint_w_s(fp0, cpu_env, fp0);
+ gen_store_fpr32(fp0, a->fd);
+
+ tcg_temp_free_i32(fp0);
+
+ return true;
+}
+
+static bool trans_ftint_w_d(DisasContext *ctx, arg_ftint_w_d *a)
+{
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr64(fp64, a->fj);
+ gen_helper_fp_tint_w_d(fp32, cpu_env, fp64);
+ gen_store_fpr32(fp32, a->fd);
+
+ tcg_temp_free_i32(fp32);
+ tcg_temp_free_i64(fp64);
+
+ return true;
+}
+
+static bool trans_ftint_l_s(DisasContext *ctx, arg_ftint_l_s *a)
+{
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr32(fp32, a->fj);
+ gen_helper_fp_tint_l_s(fp64, cpu_env, fp32);
+ gen_store_fpr64(fp64, a->fd);
+
+ tcg_temp_free_i32(fp32);
+ tcg_temp_free_i64(fp64);
+
+ return true;
+}
+
+static bool trans_ftint_l_d(DisasContext *ctx, arg_ftint_l_d *a)
+{
+ TCGv_i64 fp0;
+
+ fp0 = tcg_temp_new_i64();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr64(fp0, a->fj);
+ gen_helper_fp_tint_l_d(fp0, cpu_env, fp0);
+ gen_store_fpr64(fp0, a->fd);
+
+ tcg_temp_free_i64(fp0);
+
+ return true;
+}
+
+static bool trans_ffint_s_w(DisasContext *ctx, arg_ffint_s_w *a)
+{
+ TCGv_i32 fp0;
+
+ fp0 = tcg_temp_new_i32();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr32(fp0, a->fj);
+ gen_helper_fp_fint_s_w(fp0, cpu_env, fp0);
+ gen_store_fpr32(fp0, a->fd);
+
+ tcg_temp_free_i32(fp0);
+
+ return true;
+}
+
+static bool trans_ffint_s_l(DisasContext *ctx, arg_ffint_s_l *a)
+{
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr64(fp64, a->fj);
+ gen_helper_fp_fint_s_l(fp32, cpu_env, fp64);
+ gen_store_fpr32(fp32, a->fd);
+
+ tcg_temp_free_i32(fp32);
+ tcg_temp_free_i64(fp64);
+
+ return true;
+}
+
+static bool trans_ffint_d_w(DisasContext *ctx, arg_ffint_d_w *a)
+{
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr32(fp32, a->fj);
+ gen_helper_fp_fint_d_w(fp64, cpu_env, fp32);
+ gen_store_fpr64(fp64, a->fd);
+
+ tcg_temp_free_i32(fp32);
+ tcg_temp_free_i64(fp64);
+
+ return true;
+}
+
+static bool trans_ffint_d_l(DisasContext *ctx, arg_ffint_d_l *a)
+{
+ TCGv_i64 fp0;
+
+ fp0 = tcg_temp_new_i64();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr64(fp0, a->fj);
+ gen_helper_fp_fint_d_l(fp0, cpu_env, fp0);
+ gen_store_fpr64(fp0, a->fd);
+
+ tcg_temp_free_i64(fp0);
+
+ return true;
+}
+
+static bool trans_frint_s(DisasContext *ctx, arg_frint_s *a)
+{
+ TCGv_i32 fp0;
+
+ fp0 = tcg_temp_new_i32();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr32(fp0, a->fj);
+ gen_helper_fp_rint_s(fp0, cpu_env, fp0);
+ gen_store_fpr32(fp0, a->fd);
+
+ tcg_temp_free_i32(fp0);
+
+ return true;
+}
+
+static bool trans_frint_d(DisasContext *ctx, arg_frint_d *a)
+{
+ TCGv_i64 fp0;
+
+ fp0 = tcg_temp_new_i64();
+
+ check_fpu_enabled(ctx);
+ gen_load_fpr64(fp0, a->fj);
+ gen_helper_fp_rint_d(fp0, cpu_env, fp0);
+ gen_store_fpr64(fp0, a->fd);
+
+ tcg_temp_free_i64(fp0);
+
+ return true;
+}
--
1.8.3.1
- [PATCH v2 12/22] target/loongarch: Add fixed point extra instruction translation, (continued)
[PATCH v2 13/22] target/loongarch: Add floating point arithmetic instruction translation, Song Gao, 2021/07/21
[PATCH v2 15/22] target/loongarch: Add floating point conversion instruction translation,
Song Gao <=
[PATCH v2 14/22] target/loongarch: Add floating point comparison instruction translation, Song Gao, 2021/07/21
[PATCH v2 16/22] target/loongarch: Add floating point move instruction translation, Song Gao, 2021/07/21
[PATCH v2 18/22] target/loongarch: Add branch instruction translation, Song Gao, 2021/07/21