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Re: [PATCH v3 10/13] target/riscv: Reduce riscv_tr_breakpoint_check pc a
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From: |
Peter Maydell |
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Subject: |
Re: [PATCH v3 10/13] target/riscv: Reduce riscv_tr_breakpoint_check pc advance to 2 |
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Date: |
Sun, 18 Jul 2021 19:16:18 +0100 |
On Sun, 18 Jul 2021 at 19:02, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 7/17/21 1:35 PM, Peter Maydell wrote:
> > (What goes wrong if we just say "always use a TB size of 1 regardless
> > of target arch" rather than having the arch return the worst case
> > minimum insn length?)
>
> Hmm, possibly nothing. Perhaps I should try that and see what happens...
Some of the comments in these patches suggest it might trigger
the warning in the disassembler about length mismatches; possibly
also you might get duff (truncated) disassembly output? I suspect
that's probably the extent of the problem. I guess these days the
plugin API might get confused -- does it treat one of these
nothing-there TBs as "nothing there" or does it try to work with
the possibly-half-an-insn ?
-- PMM
- Re: [PATCH v3 08/13] target/avr: Advance pc in avr_tr_breakpoint_check, (continued)
- [PATCH v3 12/13] accel/tcg: Hoist tb_cflags to a local in translator_loop, Richard Henderson, 2021/07/17
- [PATCH v3 03/13] accel/tcg: Add CF_NO_GOTO_TB and CF_NO_GOTO_PTR, Richard Henderson, 2021/07/17
- [PATCH v3 13/13] accel/tcg: Encode breakpoint info into tb->cflags, Richard Henderson, 2021/07/17
- [PATCH v3 11/13] accel/tcg: Adjust interface of TranslatorOps.breakpoint_check, Richard Henderson, 2021/07/17
- [PATCH v3 10/13] target/riscv: Reduce riscv_tr_breakpoint_check pc advance to 2, Richard Henderson, 2021/07/17