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Re: [PATCH 13/17] target/riscv: Use gpr_{src,dst} for RVD
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From: |
Alistair Francis |
|
Subject: |
Re: [PATCH 13/17] target/riscv: Use gpr_{src,dst} for RVD |
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Date: |
Thu, 15 Jul 2021 15:00:39 +1000 |
On Fri, Jul 9, 2021 at 2:42 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvd.c.inc | 116 +++++++++---------------
> 1 file changed, 44 insertions(+), 72 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvd.c.inc
> b/target/riscv/insn_trans/trans_rvd.c.inc
> index 7e45538ae0..9bb15fdc12 100644
> --- a/target/riscv/insn_trans/trans_rvd.c.inc
> +++ b/target/riscv/insn_trans/trans_rvd.c.inc
> @@ -22,14 +22,22 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
> {
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVD);
> - TCGv t0 = tcg_temp_new();
> - gen_get_gpr(t0, a->rs1);
> - tcg_gen_addi_tl(t0, t0, a->imm);
>
> - tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
> + TCGv addr = gpr_src(ctx, a->rs1);
> + TCGv temp = NULL;
>
> + if (a->imm) {
> + temp = tcg_temp_new();
> + tcg_gen_addi_tl(temp, addr, a->imm);
> + addr = temp;
> + }
> +
> + tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEQ);
> +
> + if (temp) {
> + tcg_temp_free(temp);
> + }
> mark_fs_dirty(ctx);
> - tcg_temp_free(t0);
> return true;
> }
>
> @@ -37,13 +45,21 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
> {
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVD);
> - TCGv t0 = tcg_temp_new();
> - gen_get_gpr(t0, a->rs1);
> - tcg_gen_addi_tl(t0, t0, a->imm);
>
> - tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
> + TCGv addr = gpr_src(ctx, a->rs1);
> + TCGv temp = NULL;
>
> - tcg_temp_free(t0);
> + if (a->imm) {
> + temp = tcg_temp_new();
> + tcg_gen_addi_tl(temp, addr, a->imm);
> + addr = temp;
> + }
> +
> + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEQ);
> +
> + if (temp) {
> + tcg_temp_free(temp);
> + }
> return true;
> }
>
> @@ -252,11 +268,8 @@ static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a)
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVD);
>
> - TCGv t0 = tcg_temp_new();
> - gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> - gen_set_gpr(a->rd, t0);
> - tcg_temp_free(t0);
> -
> + gen_helper_feq_d(gpr_dst(ctx, a->rd), cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> return true;
> }
>
> @@ -265,11 +278,8 @@ static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a)
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVD);
>
> - TCGv t0 = tcg_temp_new();
> - gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> - gen_set_gpr(a->rd, t0);
> - tcg_temp_free(t0);
> -
> + gen_helper_flt_d(gpr_dst(ctx, a->rd), cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> return true;
> }
>
> @@ -278,11 +288,8 @@ static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a)
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVD);
>
> - TCGv t0 = tcg_temp_new();
> - gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> - gen_set_gpr(a->rd, t0);
> - tcg_temp_free(t0);
> -
> + gen_helper_fle_d(gpr_dst(ctx, a->rd), cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> return true;
> }
>
> @@ -291,10 +298,7 @@ static bool trans_fclass_d(DisasContext *ctx,
> arg_fclass_d *a)
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVD);
>
> - TCGv t0 = tcg_temp_new();
> - gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
> - gen_set_gpr(a->rd, t0);
> - tcg_temp_free(t0);
> + gen_helper_fclass_d(gpr_dst(ctx, a->rd), cpu_fpr[a->rs1]);
> return true;
> }
>
> @@ -303,12 +307,8 @@ static bool trans_fcvt_w_d(DisasContext *ctx,
> arg_fcvt_w_d *a)
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVD);
>
> - TCGv t0 = tcg_temp_new();
> gen_set_rm(ctx, a->rm);
> - gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]);
> - gen_set_gpr(a->rd, t0);
> - tcg_temp_free(t0);
> -
> + gen_helper_fcvt_w_d(gpr_dst(ctx, a->rd), cpu_env, cpu_fpr[a->rs1]);
> return true;
> }
>
> @@ -317,12 +317,8 @@ static bool trans_fcvt_wu_d(DisasContext *ctx,
> arg_fcvt_wu_d *a)
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVD);
>
> - TCGv t0 = tcg_temp_new();
> gen_set_rm(ctx, a->rm);
> - gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]);
> - gen_set_gpr(a->rd, t0);
> - tcg_temp_free(t0);
> -
> + gen_helper_fcvt_wu_d(gpr_dst(ctx, a->rd), cpu_env, cpu_fpr[a->rs1]);
> return true;
> }
>
> @@ -331,12 +327,8 @@ static bool trans_fcvt_d_w(DisasContext *ctx,
> arg_fcvt_d_w *a)
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVD);
>
> - TCGv t0 = tcg_temp_new();
> - gen_get_gpr(t0, a->rs1);
> -
> gen_set_rm(ctx, a->rm);
> - gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0);
> - tcg_temp_free(t0);
> + gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, gpr_src(ctx, a->rs1));
>
> mark_fs_dirty(ctx);
> return true;
> @@ -347,12 +339,8 @@ static bool trans_fcvt_d_wu(DisasContext *ctx,
> arg_fcvt_d_wu *a)
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVD);
>
> - TCGv t0 = tcg_temp_new();
> - gen_get_gpr(t0, a->rs1);
> -
> gen_set_rm(ctx, a->rm);
> - gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0);
> - tcg_temp_free(t0);
> + gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, gpr_src(ctx, a->rs1));
>
> mark_fs_dirty(ctx);
> return true;
> @@ -364,11 +352,8 @@ static bool trans_fcvt_l_d(DisasContext *ctx,
> arg_fcvt_l_d *a)
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVD);
>
> - TCGv t0 = tcg_temp_new();
> gen_set_rm(ctx, a->rm);
> - gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]);
> - gen_set_gpr(a->rd, t0);
> - tcg_temp_free(t0);
> + gen_helper_fcvt_l_d(gpr_dst(ctx, a->rd), cpu_env, cpu_fpr[a->rs1]);
> return true;
> }
>
> @@ -378,11 +363,8 @@ static bool trans_fcvt_lu_d(DisasContext *ctx,
> arg_fcvt_lu_d *a)
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVD);
>
> - TCGv t0 = tcg_temp_new();
> gen_set_rm(ctx, a->rm);
> - gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]);
> - gen_set_gpr(a->rd, t0);
> - tcg_temp_free(t0);
> + gen_helper_fcvt_lu_d(gpr_dst(ctx, a->rd), cpu_env, cpu_fpr[a->rs1]);
> return true;
> }
>
> @@ -406,12 +388,9 @@ static bool trans_fcvt_d_l(DisasContext *ctx,
> arg_fcvt_d_l *a)
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVD);
>
> - TCGv t0 = tcg_temp_new();
> - gen_get_gpr(t0, a->rs1);
> -
> gen_set_rm(ctx, a->rm);
> - gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0);
> - tcg_temp_free(t0);
> + gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, gpr_src(ctx, a->rs1));
> +
> mark_fs_dirty(ctx);
> return true;
> }
> @@ -422,12 +401,9 @@ static bool trans_fcvt_d_lu(DisasContext *ctx,
> arg_fcvt_d_lu *a)
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVD);
>
> - TCGv t0 = tcg_temp_new();
> - gen_get_gpr(t0, a->rs1);
> -
> gen_set_rm(ctx, a->rm);
> - gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0);
> - tcg_temp_free(t0);
> + gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, gpr_src(ctx, a->rs1));
> +
> mark_fs_dirty(ctx);
> return true;
> }
> @@ -439,11 +415,7 @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x
> *a)
> REQUIRE_EXT(ctx, RVD);
>
> #ifdef TARGET_RISCV64
> - TCGv t0 = tcg_temp_new();
> - gen_get_gpr(t0, a->rs1);
> -
> - tcg_gen_mov_tl(cpu_fpr[a->rd], t0);
> - tcg_temp_free(t0);
> + tcg_gen_mov_tl(cpu_fpr[a->rd], gpr_src(ctx, a->rs1));
> mark_fs_dirty(ctx);
> return true;
> #else
> --
> 2.25.1
>
>
- [PATCH 07/17] target/riscv: Use gpr_{src,dst} for integer load/store, (continued)
- [PATCH 07/17] target/riscv: Use gpr_{src,dst} for integer load/store, Richard Henderson, 2021/07/09
- [PATCH 08/17] target/riscv: Use gpr_{src, dst} for word shift operations, Richard Henderson, 2021/07/09
- [PATCH 09/17] target/riscv: Reorg csr instructions, Richard Henderson, 2021/07/09
- [PATCH 11/17] target/riscv: Use gpr_{src,dst} for RVB, Richard Henderson, 2021/07/09
- [PATCH 12/17] target/riscv: Use gpr_{src,dst} for RVF, Richard Henderson, 2021/07/09
- [PATCH 13/17] target/riscv: Use gpr_{src,dst} for RVD, Richard Henderson, 2021/07/09
- Re: [PATCH 13/17] target/riscv: Use gpr_{src,dst} for RVD,
Alistair Francis <=
- [PATCH 15/17] target/riscv: Use gen_arith for mulh and mulhu, Richard Henderson, 2021/07/09
- [PATCH 17/17] target/riscv: Remove gen_get_gpr, Richard Henderson, 2021/07/09
- Re: [PATCH 00/17] target/riscv: Use tcg_constant_*, LIU Zhiwei, 2021/07/15