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[PULL 09/14] target/openrisc: Use tcg_constant_*
From: |
Richard Henderson |
Subject: |
[PULL 09/14] target/openrisc: Use tcg_constant_* |
Date: |
Tue, 13 Jul 2021 09:42:06 -0700 |
Replace uses of tcg_const_* allocate and free close together
with tcg_constant_*.
Reviewed-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/openrisc/translate.c | 42 ++++++++-----------------------------
1 file changed, 9 insertions(+), 33 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 37c3e3e0a3..1e3b019c59 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -129,9 +129,7 @@ void openrisc_translate_init(void)
static void gen_exception(DisasContext *dc, unsigned int excp)
{
- TCGv_i32 tmp = tcg_const_i32(excp);
- gen_helper_exception(cpu_env, tmp);
- tcg_temp_free_i32(tmp);
+ gen_helper_exception(cpu_env, tcg_constant_i32(excp));
}
static void gen_illegal_exception(DisasContext *dc)
@@ -538,13 +536,11 @@ static bool trans_l_extbz(DisasContext *dc, arg_da *a)
static bool trans_l_cmov(DisasContext *dc, arg_dab *a)
{
- TCGv zero;
+ TCGv zero = tcg_constant_tl(0);
check_r0_write(dc, a->d);
- zero = tcg_const_tl(0);
tcg_gen_movcond_tl(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, zero,
cpu_R(dc, a->a), cpu_R(dc, a->b));
- tcg_temp_free(zero);
return true;
}
@@ -632,15 +628,11 @@ static bool trans_l_jal(DisasContext *dc, arg_l_jal *a)
static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond)
{
target_ulong tmp_pc = dc->base.pc_next + a->n * 4;
- TCGv t_next = tcg_const_tl(dc->base.pc_next + 8);
- TCGv t_true = tcg_const_tl(tmp_pc);
- TCGv t_zero = tcg_const_tl(0);
+ TCGv t_next = tcg_constant_tl(dc->base.pc_next + 8);
+ TCGv t_true = tcg_constant_tl(tmp_pc);
+ TCGv t_zero = tcg_constant_tl(0);
tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, t_zero, t_true, t_next);
-
- tcg_temp_free(t_next);
- tcg_temp_free(t_true);
- tcg_temp_free(t_zero);
dc->delayed_branch = 2;
}
@@ -813,44 +805,28 @@ static bool trans_l_adrp(DisasContext *dc, arg_l_adrp *a)
static bool trans_l_addi(DisasContext *dc, arg_rri *a)
{
- TCGv t0;
-
check_r0_write(dc, a->d);
- t0 = tcg_const_tl(a->i);
- gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), t0);
- tcg_temp_free(t0);
+ gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_tl(a->i));
return true;
}
static bool trans_l_addic(DisasContext *dc, arg_rri *a)
{
- TCGv t0;
-
check_r0_write(dc, a->d);
- t0 = tcg_const_tl(a->i);
- gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), t0);
- tcg_temp_free(t0);
+ gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_tl(a->i));
return true;
}
static bool trans_l_muli(DisasContext *dc, arg_rri *a)
{
- TCGv t0;
-
check_r0_write(dc, a->d);
- t0 = tcg_const_tl(a->i);
- gen_mul(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), t0);
- tcg_temp_free(t0);
+ gen_mul(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_tl(a->i));
return true;
}
static bool trans_l_maci(DisasContext *dc, arg_l_maci *a)
{
- TCGv t0;
-
- t0 = tcg_const_tl(a->i);
- gen_mac(dc, cpu_R(dc, a->a), t0);
- tcg_temp_free(t0);
+ gen_mac(dc, cpu_R(dc, a->a), tcg_constant_tl(a->i));
return true;
}
--
2.25.1
- [PULL 01/14] target/i386: Tidy hw_breakpoint_remove, (continued)
- [PULL 01/14] target/i386: Tidy hw_breakpoint_remove, Richard Henderson, 2021/07/13
- [PULL 03/14] target/i386: Split out do_fninit, Richard Henderson, 2021/07/13
- [PULL 02/14] target/i386: Trivial code motion and code style fix, Richard Henderson, 2021/07/13
- [PULL 05/14] target/alpha: Store set into rx flag, Richard Henderson, 2021/07/13
- [PULL 06/14] target/alpha: Use dest_sink for HW_RET temporary, Richard Henderson, 2021/07/13
- [PULL 04/14] target/i386: Correct implementation for FCS, FIP, FDS and FDP, Richard Henderson, 2021/07/13
- [PULL 07/14] target/alpha: Use tcg_constant_i64 for zero and lit, Richard Henderson, 2021/07/13
- [PULL 11/14] target/openrisc: Cache constant 0 in DisasContext, Richard Henderson, 2021/07/13
- [PULL 08/14] target/alpha: Use tcg_constant_* elsewhere, Richard Henderson, 2021/07/13
- [PULL 10/14] target/openrisc: Use tcg_constant_tl for dc->R0, Richard Henderson, 2021/07/13
- [PULL 09/14] target/openrisc: Use tcg_constant_*,
Richard Henderson <=
- [PULL 12/14] target/openrisc: Use dc->zero in gen_add, gen_addc, Richard Henderson, 2021/07/13
- [PULL 14/14] target/hppa: Clean up DisasCond, Richard Henderson, 2021/07/13
- [PULL 13/14] target/hppa: Use tcg_constant_*, Richard Henderson, 2021/07/13
- Re: [PULL 00/14] misc translator patch queue, Peter Maydell, 2021/07/14