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[PULL 08/14] target/alpha: Use tcg_constant_* elsewhere
From: |
Richard Henderson |
Subject: |
[PULL 08/14] target/alpha: Use tcg_constant_* elsewhere |
Date: |
Tue, 13 Jul 2021 09:42:05 -0700 |
Replace the remaining uses of tcg_const_*. These uses are
all local, with the allocate and free close together.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/alpha/translate.c | 46 ++++++++++++----------------------------
1 file changed, 14 insertions(+), 32 deletions(-)
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 58c0e08c0c..103c6326a2 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -250,11 +250,9 @@ static void gen_excp_1(int exception, int error_code)
{
TCGv_i32 tmp1, tmp2;
- tmp1 = tcg_const_i32(exception);
- tmp2 = tcg_const_i32(error_code);
+ tmp1 = tcg_constant_i32(exception);
+ tmp2 = tcg_constant_i32(error_code);
gen_helper_excp(cpu_env, tmp1, tmp2);
- tcg_temp_free_i32(tmp2);
- tcg_temp_free_i32(tmp1);
}
static DisasJumpType gen_excp(DisasContext *ctx, int exception, int error_code)
@@ -474,15 +472,11 @@ static DisasJumpType gen_bcond_internal(DisasContext
*ctx, TCGCond cond,
return DISAS_NORETURN;
} else {
- TCGv_i64 z = tcg_const_i64(0);
- TCGv_i64 d = tcg_const_i64(dest);
- TCGv_i64 p = tcg_const_i64(ctx->base.pc_next);
+ TCGv_i64 z = load_zero(ctx);
+ TCGv_i64 d = tcg_constant_i64(dest);
+ TCGv_i64 p = tcg_constant_i64(ctx->base.pc_next);
tcg_gen_movcond_i64(cond, cpu_pc, cmp, z, d, p);
-
- tcg_temp_free_i64(z);
- tcg_temp_free_i64(d);
- tcg_temp_free_i64(p);
return DISAS_PC_UPDATED;
}
}
@@ -684,22 +678,19 @@ static void gen_fp_exc_raise(int rc, int fn11)
if (!(fn11 & QUAL_I)) {
ignore |= FPCR_INE;
}
- ign = tcg_const_i32(ignore);
+ ign = tcg_constant_i32(ignore);
/* ??? Pass in the regno of the destination so that the helper can
set EXC_MASK, which contains a bitmask of destination registers
that have caused arithmetic traps. A simple userspace emulation
does not require this. We do need it for a guest kernel's entArith,
or if we were to do something clever with imprecise exceptions. */
- reg = tcg_const_i32(rc + 32);
+ reg = tcg_constant_i32(rc + 32);
if (fn11 & QUAL_S) {
gen_helper_fp_exc_raise_s(cpu_env, ign, reg);
} else {
gen_helper_fp_exc_raise(cpu_env, ign, reg);
}
-
- tcg_temp_free_i32(reg);
- tcg_temp_free_i32(ign);
}
static void gen_cvtlq(TCGv vc, TCGv vb)
@@ -792,7 +783,7 @@ IEEE_INTCVT(cvtqt)
static void gen_cpy_mask(TCGv vc, TCGv va, TCGv vb, bool inv_a, uint64_t mask)
{
- TCGv vmask = tcg_const_i64(mask);
+ TCGv vmask = tcg_constant_i64(mask);
TCGv tmp = tcg_temp_new_i64();
if (inv_a) {
@@ -804,7 +795,6 @@ static void gen_cpy_mask(TCGv vc, TCGv va, TCGv vb, bool
inv_a, uint64_t mask)
tcg_gen_andc_i64(vc, vb, vmask);
tcg_gen_or_i64(vc, vc, tmp);
- tcg_temp_free(vmask);
tcg_temp_free(tmp);
}
@@ -1178,12 +1168,9 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int
palcode)
case 0x3E:
/* WTINT */
- {
- TCGv_i32 tmp = tcg_const_i32(1);
- tcg_gen_st_i32(tmp, cpu_env, -offsetof(AlphaCPU, env) +
- offsetof(CPUState, halted));
- tcg_temp_free_i32(tmp);
- }
+ tcg_gen_st_i32(tcg_constant_i32(1), cpu_env,
+ -offsetof(AlphaCPU, env) +
+ offsetof(CPUState, halted));
tcg_gen_movi_i64(ctx->ir[IR_V0], 0);
return gen_excp(ctx, EXCP_HALTED, 0);
@@ -1334,12 +1321,8 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv
vb, int regno)
case 253:
/* WAIT */
- {
- TCGv_i32 tmp = tcg_const_i32(1);
- tcg_gen_st_i32(tmp, cpu_env, -offsetof(AlphaCPU, env) +
- offsetof(CPUState, halted));
- tcg_temp_free_i32(tmp);
- }
+ tcg_gen_st_i32(tcg_constant_i32(1), cpu_env,
+ -offsetof(AlphaCPU, env) + offsetof(CPUState, halted));
return gen_excp(ctx, EXCP_HALTED, 0);
case 252:
@@ -2712,9 +2695,8 @@ static DisasJumpType translate_one(DisasContext *ctx,
uint32_t insn)
vb = load_gpr(ctx, rb);
}
tcg_gen_movi_i64(cpu_lock_addr, -1);
+ st_flag_byte(load_zero(ctx), ENV_FLAG_RX_SHIFT);
tmp = tcg_temp_new();
- tcg_gen_movi_i64(tmp, 0);
- st_flag_byte(tmp, ENV_FLAG_RX_SHIFT);
tcg_gen_andi_i64(tmp, vb, 1);
st_flag_byte(tmp, ENV_FLAG_PAL_SHIFT);
tcg_temp_free(tmp);
--
2.25.1
- [PULL 00/14] misc translator patch queue, Richard Henderson, 2021/07/13
- [PULL 01/14] target/i386: Tidy hw_breakpoint_remove, Richard Henderson, 2021/07/13
- [PULL 03/14] target/i386: Split out do_fninit, Richard Henderson, 2021/07/13
- [PULL 02/14] target/i386: Trivial code motion and code style fix, Richard Henderson, 2021/07/13
- [PULL 05/14] target/alpha: Store set into rx flag, Richard Henderson, 2021/07/13
- [PULL 06/14] target/alpha: Use dest_sink for HW_RET temporary, Richard Henderson, 2021/07/13
- [PULL 04/14] target/i386: Correct implementation for FCS, FIP, FDS and FDP, Richard Henderson, 2021/07/13
- [PULL 07/14] target/alpha: Use tcg_constant_i64 for zero and lit, Richard Henderson, 2021/07/13
- [PULL 11/14] target/openrisc: Cache constant 0 in DisasContext, Richard Henderson, 2021/07/13
- [PULL 08/14] target/alpha: Use tcg_constant_* elsewhere,
Richard Henderson <=
- [PULL 10/14] target/openrisc: Use tcg_constant_tl for dc->R0, Richard Henderson, 2021/07/13
- [PULL 09/14] target/openrisc: Use tcg_constant_*, Richard Henderson, 2021/07/13
- [PULL 12/14] target/openrisc: Use dc->zero in gen_add, gen_addc, Richard Henderson, 2021/07/13
- [PULL 14/14] target/hppa: Clean up DisasCond, Richard Henderson, 2021/07/13
- [PULL 13/14] target/hppa: Use tcg_constant_*, Richard Henderson, 2021/07/13
- Re: [PULL 00/14] misc translator patch queue, Peter Maydell, 2021/07/14