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[PULL 30/63] tcg: Add tcg_gen_vec_add{sub}8_i32
From: |
Richard Henderson |
Subject: |
[PULL 30/63] tcg: Add tcg_gen_vec_add{sub}8_i32 |
Date: |
Tue, 29 Jun 2021 11:54:22 -0700 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Implement tcg_gen_vec_add{sub}8_tl by adding corresponging i32 OP.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20210624105023.3852-3-zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-op-gvec.h | 6 ++++++
tcg/tcg-op-gvec.c | 38 ++++++++++++++++++++++++++++++++++++++
2 files changed, 44 insertions(+)
diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
index 9b67822f54..2d5ad6ce12 100644
--- a/include/tcg/tcg-op-gvec.h
+++ b/include/tcg/tcg-op-gvec.h
@@ -402,14 +402,20 @@ void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a,
int64_t c);
void tcg_gen_vec_rotl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c);
/* 32-bit vector operations. */
+void tcg_gen_vec_add8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
void tcg_gen_vec_add16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
+void tcg_gen_vec_sub8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
void tcg_gen_vec_sub16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
#if TARGET_LONG_BITS == 64
+#define tcg_gen_vec_add8_tl tcg_gen_vec_add8_i64
+#define tcg_gen_vec_sub8_tl tcg_gen_vec_sub8_i64
#define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i64
#define tcg_gen_vec_sub16_tl tcg_gen_vec_sub16_i64
#else
+#define tcg_gen_vec_add8_tl tcg_gen_vec_add8_i32
+#define tcg_gen_vec_sub8_tl tcg_gen_vec_sub8_i32
#define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i32
#define tcg_gen_vec_sub16_tl tcg_gen_vec_sub16_i32
#endif
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 7ddd56c0e6..6d9a0aed62 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -1736,6 +1736,25 @@ void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a,
TCGv_i64 b)
gen_addv_mask(d, a, b, m);
}
+void tcg_gen_vec_add8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i32 m = tcg_constant_i32((int32_t)dup_const(MO_8, 0x80));
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ TCGv_i32 t3 = tcg_temp_new_i32();
+
+ tcg_gen_andc_i32(t1, a, m);
+ tcg_gen_andc_i32(t2, b, m);
+ tcg_gen_xor_i32(t3, a, b);
+ tcg_gen_add_i32(d, t1, t2);
+ tcg_gen_and_i32(t3, t3, m);
+ tcg_gen_xor_i32(d, d, t3);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t3);
+}
+
void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000));
@@ -1900,6 +1919,25 @@ void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a,
TCGv_i64 b)
gen_subv_mask(d, a, b, m);
}
+void tcg_gen_vec_sub8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i32 m = tcg_constant_i32((int32_t)dup_const(MO_8, 0x80));
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ TCGv_i32 t3 = tcg_temp_new_i32();
+
+ tcg_gen_or_i32(t1, a, m);
+ tcg_gen_andc_i32(t2, b, m);
+ tcg_gen_eqv_i32(t3, a, b);
+ tcg_gen_sub_i32(d, t1, t2);
+ tcg_gen_and_i32(t3, t3, m);
+ tcg_gen_xor_i32(d, d, t3);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t3);
+}
+
void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000));
--
2.25.1
- [PULL 18/63] target/cris: Convert to TranslatorOps, (continued)
- [PULL 18/63] target/cris: Convert to TranslatorOps, Richard Henderson, 2021/06/29
- [PULL 11/63] target/avr: Change ctx to DisasContext* in gen_intermediate_code, Richard Henderson, 2021/06/29
- [PULL 20/63] target/cris: Mark static arrays const, Richard Henderson, 2021/06/29
- [PULL 27/63] target/cris: Remove dc->flagx_known, Richard Henderson, 2021/06/29
- [PULL 26/63] target/cris: Improve JMP_INDIRECT, Richard Henderson, 2021/06/29
- [PULL 23/63] target/cris: Add DISAS_UPDATE_NEXT, Richard Henderson, 2021/06/29
- [PULL 21/63] target/cris: Fold unhandled X_FLAG changes into cpustate_changed, Richard Henderson, 2021/06/29
- [PULL 24/63] target/cris: Add DISAS_DBRANCH, Richard Henderson, 2021/06/29
- [PULL 10/63] target/avr: Add DisasContextBase to DisasContext, Richard Henderson, 2021/06/29
- [PULL 14/63] target/cris: Remove DISAS_SWI, Richard Henderson, 2021/06/29
- [PULL 30/63] tcg: Add tcg_gen_vec_add{sub}8_i32,
Richard Henderson <=
- [PULL 25/63] target/cris: Use tcg_gen_lookup_and_goto_ptr, Richard Henderson, 2021/06/29
- [PULL 31/63] tcg: Add tcg_gen_vec_shl{shr}{sar}16i_i32, Richard Henderson, 2021/06/29
- [PULL 32/63] tcg: Add tcg_gen_vec_shl{shr}{sar}8i_i32, Richard Henderson, 2021/06/29
- [PULL 28/63] target/cris: Do not exit tb for X_FLAG changes, Richard Henderson, 2021/06/29
- [PULL 35/63] tcg: Add flags argument to bswap opcodes, Richard Henderson, 2021/06/29
- [PULL 34/63] tcg: Use correct trap number for page faults on *BSD systems, Richard Henderson, 2021/06/29
- [PULL 16/63] target/cris: Mark exceptions as DISAS_NORETURN, Richard Henderson, 2021/06/29
- [PULL 36/63] tcg/i386: Support bswap flags, Richard Henderson, 2021/06/29
- [PULL 38/63] tcg/aarch64: Support bswap flags, Richard Henderson, 2021/06/29
- [PULL 39/63] tcg/arm: Support bswap flags, Richard Henderson, 2021/06/29