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[PULL 16/57] target/arm: Implement MVE VREV16, VREV32, VREV64
From: |
Peter Maydell |
Subject: |
[PULL 16/57] target/arm: Implement MVE VREV16, VREV32, VREV64 |
Date: |
Mon, 21 Jun 2021 17:27:52 +0100 |
Implement the MVE instructions VREV16, VREV32 and VREV64.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-6-peter.maydell@linaro.org
---
target/arm/helper-mve.h | 7 +++++++
target/arm/mve.decode | 4 ++++
target/arm/mve_helper.c | 7 +++++++
target/arm/translate-mve.c | 33 +++++++++++++++++++++++++++++++++
4 files changed, 51 insertions(+)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index bdd6675ea14..4c89387587d 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -40,3 +40,10 @@ DEF_HELPER_FLAGS_3(mve_vclsw, TCG_CALL_NO_WG, void, env,
ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vclzb, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vclzh, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vclzw, TCG_CALL_NO_WG, void, env, ptr, ptr)
+
+DEF_HELPER_FLAGS_3(mve_vrev16b, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vrev32b, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vrev32h, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vrev64b, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vrev64h, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vrev64w, TCG_CALL_NO_WG, void, env, ptr, ptr)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index adceef91597..16ee511a5cb 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -70,3 +70,7 @@ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110
....... @vldr_vstr \
VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op
VCLZ 1111 1111 1 . 11 .. 00 ... 0 0100 11 . 0 ... 0 @1op
+
+VREV16 1111 1111 1 . 11 .. 00 ... 0 0001 01 . 0 ... 0 @1op
+VREV32 1111 1111 1 . 11 .. 00 ... 0 0000 11 . 0 ... 0 @1op
+VREV64 1111 1111 1 . 11 .. 00 ... 0 0000 01 . 0 ... 0 @1op
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index ba01ea3bcd0..8b565b50a9a 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -270,3 +270,10 @@ DO_1OP(vclsw, 4, int32_t, clrsb32)
DO_1OP(vclzb, 1, uint8_t, DO_CLZ_B)
DO_1OP(vclzh, 2, uint16_t, DO_CLZ_H)
DO_1OP(vclzw, 4, uint32_t, clz32)
+
+DO_1OP(vrev16b, 2, uint16_t, bswap16)
+DO_1OP(vrev32b, 4, uint32_t, bswap32)
+DO_1OP(vrev32h, 4, uint32_t, hswap32)
+DO_1OP(vrev64b, 8, uint64_t, bswap64)
+DO_1OP(vrev64h, 8, uint64_t, hswap64)
+DO_1OP(vrev64w, 8, uint64_t, wswap64)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 4e5d032242b..32a8324c5e6 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -199,3 +199,36 @@ static bool do_1op(DisasContext *s, arg_1op *a,
MVEGenOneOpFn fn)
DO_1OP(VCLZ, vclz)
DO_1OP(VCLS, vcls)
+
+static bool trans_VREV16(DisasContext *s, arg_1op *a)
+{
+ static MVEGenOneOpFn * const fns[] = {
+ gen_helper_mve_vrev16b,
+ NULL,
+ NULL,
+ NULL,
+ };
+ return do_1op(s, a, fns[a->size]);
+}
+
+static bool trans_VREV32(DisasContext *s, arg_1op *a)
+{
+ static MVEGenOneOpFn * const fns[] = {
+ gen_helper_mve_vrev32b,
+ gen_helper_mve_vrev32h,
+ NULL,
+ NULL,
+ };
+ return do_1op(s, a, fns[a->size]);
+}
+
+static bool trans_VREV64(DisasContext *s, arg_1op *a)
+{
+ static MVEGenOneOpFn * const fns[] = {
+ gen_helper_mve_vrev64b,
+ gen_helper_mve_vrev64h,
+ gen_helper_mve_vrev64w,
+ NULL,
+ };
+ return do_1op(s, a, fns[a->size]);
+}
--
2.20.1
- [PULL 04/57] docs/system/arm: Document which architecture extensions we emulate, (continued)
- [PULL 04/57] docs/system/arm: Document which architecture extensions we emulate, Peter Maydell, 2021/06/21
- [PULL 05/57] target/arm/translate-vfp.c: Whitespace fixes, Peter Maydell, 2021/06/21
- [PULL 06/57] target/arm: Handle FPU being disabled in FPCXT_NS accesses, Peter Maydell, 2021/06/21
- [PULL 03/57] target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors, Peter Maydell, 2021/06/21
- [PULL 10/57] target/arm: Split vfp_access_check() into A and M versions, Peter Maydell, 2021/06/21
- [PULL 02/57] hw/acpi: Provide function acpi_ghes_present(), Peter Maydell, 2021/06/21
- [PULL 08/57] target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access, Peter Maydell, 2021/06/21
- [PULL 11/57] target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m(), Peter Maydell, 2021/06/21
- [PULL 09/57] target/arm: Factor FP context update code out into helper function, Peter Maydell, 2021/06/21
- [PULL 15/57] target/arm: Implement MVE VCLS, Peter Maydell, 2021/06/21
- [PULL 16/57] target/arm: Implement MVE VREV16, VREV32, VREV64,
Peter Maydell <=
- [PULL 07/57] target/arm: Don't NOCP fault for FPCXT_NS accesses, Peter Maydell, 2021/06/21
- [PULL 17/57] target/arm: Implement MVE VMVN (register), Peter Maydell, 2021/06/21
- [PULL 20/57] tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64, Peter Maydell, 2021/06/21
- [PULL 12/57] target/arm: Implement MVE VLDR/VSTR (non-widening forms), Peter Maydell, 2021/06/21
- [PULL 19/57] target/arm: Implement MVE VNEG, Peter Maydell, 2021/06/21
- [PULL 21/57] target/arm: Implement MVE VDUP, Peter Maydell, 2021/06/21
- [PULL 26/57] target/arm: Implement MVE VMAX, VMIN, Peter Maydell, 2021/06/21
- [PULL 23/57] target/arm: Implement MVE VADD, VSUB, VMUL, Peter Maydell, 2021/06/21
- [PULL 30/57] target/arm: Implement MVE VMLALDAV, Peter Maydell, 2021/06/21
- [PULL 25/57] target/arm: Implement MVE VRMULH, Peter Maydell, 2021/06/21