[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 15/57] target/arm: Implement MVE VCLS
From: |
Peter Maydell |
Subject: |
[PULL 15/57] target/arm: Implement MVE VCLS |
Date: |
Mon, 21 Jun 2021 17:27:51 +0100 |
Implement the MVE VCLS insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-5-peter.maydell@linaro.org
---
target/arm/helper-mve.h | 4 ++++
target/arm/mve.decode | 1 +
target/arm/mve_helper.c | 7 +++++++
target/arm/translate-mve.c | 1 +
4 files changed, 13 insertions(+)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index c5c1315b161..bdd6675ea14 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -33,6 +33,10 @@ DEF_HELPER_FLAGS_3(mve_vstrb_h, TCG_CALL_NO_WG, void, env,
ptr, i32)
DEF_HELPER_FLAGS_3(mve_vstrb_w, TCG_CALL_NO_WG, void, env, ptr, i32)
DEF_HELPER_FLAGS_3(mve_vstrh_w, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vclsb, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vclsh, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vclsw, TCG_CALL_NO_WG, void, env, ptr, ptr)
+
DEF_HELPER_FLAGS_3(mve_vclzb, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vclzh, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vclzw, TCG_CALL_NO_WG, void, env, ptr, ptr)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 24999bf703e..adceef91597 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -68,4 +68,5 @@ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110
....... @vldr_vstr \
# Vector miscellaneous
+VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op
VCLZ 1111 1111 1 . 11 .. 00 ... 0 0100 11 . 0 ... 0 @1op
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index f2fae523e24..ba01ea3bcd0 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -257,6 +257,13 @@ static void mergemask_sq(int64_t *d, int64_t r, uint16_t
mask)
mve_advance_vpt(env); \
}
+#define DO_CLS_B(N) (clrsb32(N) - 24)
+#define DO_CLS_H(N) (clrsb32(N) - 16)
+
+DO_1OP(vclsb, 1, int8_t, DO_CLS_B)
+DO_1OP(vclsh, 2, int16_t, DO_CLS_H)
+DO_1OP(vclsw, 4, int32_t, clrsb32)
+
#define DO_CLZ_B(N) (clz32(N) - 24)
#define DO_CLZ_H(N) (clz32(N) - 16)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 9eb6a68c976..4e5d032242b 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -198,3 +198,4 @@ static bool do_1op(DisasContext *s, arg_1op *a,
MVEGenOneOpFn fn)
}
DO_1OP(VCLZ, vclz)
+DO_1OP(VCLS, vcls)
--
2.20.1
- [PULL 01/57] hw/acpi: Provide stub version of acpi_ghes_record_errors(), (continued)
- [PULL 01/57] hw/acpi: Provide stub version of acpi_ghes_record_errors(), Peter Maydell, 2021/06/21
- [PULL 04/57] docs/system/arm: Document which architecture extensions we emulate, Peter Maydell, 2021/06/21
- [PULL 05/57] target/arm/translate-vfp.c: Whitespace fixes, Peter Maydell, 2021/06/21
- [PULL 06/57] target/arm: Handle FPU being disabled in FPCXT_NS accesses, Peter Maydell, 2021/06/21
- [PULL 03/57] target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors, Peter Maydell, 2021/06/21
- [PULL 10/57] target/arm: Split vfp_access_check() into A and M versions, Peter Maydell, 2021/06/21
- [PULL 02/57] hw/acpi: Provide function acpi_ghes_present(), Peter Maydell, 2021/06/21
- [PULL 08/57] target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access, Peter Maydell, 2021/06/21
- [PULL 11/57] target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m(), Peter Maydell, 2021/06/21
- [PULL 09/57] target/arm: Factor FP context update code out into helper function, Peter Maydell, 2021/06/21
- [PULL 15/57] target/arm: Implement MVE VCLS,
Peter Maydell <=
- [PULL 16/57] target/arm: Implement MVE VREV16, VREV32, VREV64, Peter Maydell, 2021/06/21
- [PULL 07/57] target/arm: Don't NOCP fault for FPCXT_NS accesses, Peter Maydell, 2021/06/21
- [PULL 17/57] target/arm: Implement MVE VMVN (register), Peter Maydell, 2021/06/21
- [PULL 20/57] tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64, Peter Maydell, 2021/06/21
- [PULL 12/57] target/arm: Implement MVE VLDR/VSTR (non-widening forms), Peter Maydell, 2021/06/21
- [PULL 19/57] target/arm: Implement MVE VNEG, Peter Maydell, 2021/06/21
- [PULL 21/57] target/arm: Implement MVE VDUP, Peter Maydell, 2021/06/21
- [PULL 26/57] target/arm: Implement MVE VMAX, VMIN, Peter Maydell, 2021/06/21
- [PULL 23/57] target/arm: Implement MVE VADD, VSUB, VMUL, Peter Maydell, 2021/06/21
- [PULL 30/57] target/arm: Implement MVE VMLALDAV, Peter Maydell, 2021/06/21