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[PATCH 4/6] target/microblaze: Fix Exception Status Register 'Cause' def
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From: |
Philippe Mathieu-Daudé |
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Subject: |
[PATCH 4/6] target/microblaze: Fix Exception Status Register 'Cause' definitions |
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Date: |
Thu, 3 Jun 2021 11:03:08 +0200 |
See 'MicroBlaze Processor Reference Guide' UG081 (v9.0),
Table 1-11: "Exception Status Register (ESR)".
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/microblaze/cpu.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index e4bba8a7551..42b9ad8d313 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -95,10 +95,10 @@ typedef struct CPUMBState CPUMBState;
#define ESR_EC_FPU 6
#define ESR_EC_PRIVINSN 7
#define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */
-#define ESR_EC_DATA_STORAGE 8
-#define ESR_EC_INSN_STORAGE 9
-#define ESR_EC_DATA_TLB 10
-#define ESR_EC_INSN_TLB 11
+#define ESR_EC_DATA_STORAGE 16
+#define ESR_EC_INSN_STORAGE 17
+#define ESR_EC_DATA_TLB 18
+#define ESR_EC_INSN_TLB 19
#define ESR_EC_MASK 31
/* Floating Point Status Register (FSR) Bits */
--
2.26.3
- [PATCH 0/6] target/microblaze: Clean up MMU translation failed path, Philippe Mathieu-Daudé, 2021/06/03
- [PATCH 1/6] target/microblaze: Use the IEC binary prefix definitions, Philippe Mathieu-Daudé, 2021/06/03
- [PATCH 2/6] target/microblaze: Extract FPU helpers to fpu_helper.c, Philippe Mathieu-Daudé, 2021/06/03
- [PATCH 3/6] target/microblaze: Assert transaction failures have exception enabled, Philippe Mathieu-Daudé, 2021/06/03
- [PATCH 4/6] target/microblaze: Fix Exception Status Register 'Cause' definitions,
Philippe Mathieu-Daudé <=
- [PATCH 5/6] target/microblaze: Replace magic values by proper definitions, Philippe Mathieu-Daudé, 2021/06/03
- [PATCH 6/6] target/microblaze: Set OPB bits in tlb_fill, not in transaction_failed, Philippe Mathieu-Daudé, 2021/06/03