[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v6 05/14] target/ppc: Implement PNOP
From: |
matheus . ferst |
Subject: |
[PATCH v6 05/14] target/ppc: Implement PNOP |
Date: |
Tue, 1 Jun 2021 16:35:19 -0300 |
From: Richard Henderson <richard.henderson@linaro.org>
The illegal suffix behavior matches what was observed in a
POWER10 DD2.0 machine.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn64.decode | 67 ++++++++++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 11 ++++
2 files changed, 78 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 1965088915..9aa5097a98 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -28,3 +28,70 @@
PADDI 000001 10 0--.-- .................. \
001110 ..... ..... ................ @PLS_D
+
+### Prefixed No-operation Instruction
+
+@PNOP 000001 11 0000-- 000000000000000000 \
+ ................................
+
+{
+ [
+ ## Invalid suffixes: Branch instruction
+ # bc[l][a]
+ INVALID ................................ \
+ 010000-------------------------- @PNOP
+ # b[l][a]
+ INVALID ................................ \
+ 010010-------------------------- @PNOP
+ # bclr[l]
+ INVALID ................................ \
+ 010011---------------0000010000- @PNOP
+ # bcctr[l]
+ INVALID ................................ \
+ 010011---------------1000010000- @PNOP
+ # bctar[l]
+ INVALID ................................ \
+ 010011---------------1000110000- @PNOP
+
+ ## Invalid suffixes: rfebb
+ INVALID ................................ \
+ 010011---------------0010010010- @PNOP
+
+ ## Invalid suffixes: context synchronizing other than isync
+ # sc
+ INVALID ................................ \
+ 010001------------------------1- @PNOP
+ # scv
+ INVALID ................................ \
+ 010001------------------------01 @PNOP
+ # rfscv
+ INVALID ................................ \
+ 010011---------------0001010010- @PNOP
+ # rfid
+ INVALID ................................ \
+ 010011---------------0000010010- @PNOP
+ # hrfid
+ INVALID ................................ \
+ 010011---------------0100010010- @PNOP
+ # urfid
+ INVALID ................................ \
+ 010011---------------0100110010- @PNOP
+ # stop
+ INVALID ................................ \
+ 010011---------------0101110010- @PNOP
+ # mtmsr w/ L=0
+ INVALID ................................ \
+ 011111---------0-----0010010010- @PNOP
+ # mtmsrd w/ L=0
+ INVALID ................................ \
+ 011111---------0-----0010110010- @PNOP
+
+ ## Invalid suffixes: Service Processor Attention
+ INVALID ................................ \
+ 000000----------------100000000- @PNOP
+ ]
+
+ ## Valid suffixes
+ PNOP ................................ \
+ -------------------------------- @PNOP
+}
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
b/target/ppc/translate/fixedpoint-impl.c.inc
index 344a3ed54b..ce034a14a7 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -60,3 +60,14 @@ static bool trans_ADDIS(DisasContext *ctx, arg_D *a)
a->si <<= 16;
return trans_ADDI(ctx, a);
}
+
+static bool trans_INVALID(DisasContext *ctx, arg_INVALID *a)
+{
+ gen_invalid(ctx);
+ return true;
+}
+
+static bool trans_PNOP(DisasContext *ctx, arg_PNOP *a)
+{
+ return true;
+}
--
2.25.1
- [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions, matheus . ferst, 2021/06/01
- [PATCH v6 01/14] target/ppc: Introduce macros to check isa extensions, matheus . ferst, 2021/06/01
- [PATCH v6 02/14] target/ppc: Move page crossing check to ppc_tr_translate_insn, matheus . ferst, 2021/06/01
- [PATCH v6 03/14] target/ppc: Add infrastructure for prefixed insns, matheus . ferst, 2021/06/01
- [PATCH v6 04/14] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI, matheus . ferst, 2021/06/01
- [PATCH v6 05/14] target/ppc: Implement PNOP,
matheus . ferst <=
- [PATCH v6 06/14] target/ppc: Move D/DS/X-form integer loads to decodetree, matheus . ferst, 2021/06/01
- [PATCH v6 07/14] target/ppc: Implement prefixed integer load instructions, matheus . ferst, 2021/06/01
- [PATCH v6 08/14] target/ppc: Move D/DS/X-form integer stores to decodetree, matheus . ferst, 2021/06/01
- [PATCH v6 09/14] target/ppc: Implement prefixed integer store instructions, matheus . ferst, 2021/06/01
- [PATCH v6 10/14] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions, matheus . ferst, 2021/06/01
- [PATCH v6 11/14] target/ppc: Implement cfuged instruction, matheus . ferst, 2021/06/01
- [PATCH v6 12/14] target/ppc: Implement vcfuged instruction, matheus . ferst, 2021/06/01