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[PULL 02/31] exec/memory_ldst_phys: Sort declarations
From: |
Richard Henderson |
Subject: |
[PULL 02/31] exec/memory_ldst_phys: Sort declarations |
Date: |
Wed, 26 May 2021 16:46:41 -0700 |
From: Philippe Mathieu-Daudé <philmd@redhat.com>
To ease the file review, sort the declarations by the size of
the access (8, 16, 32). Simple code movement, no logical change.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210518183655.1711377-3-philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/memory_ldst_phys.h.inc | 78 ++++++++++++++---------------
1 file changed, 39 insertions(+), 39 deletions(-)
diff --git a/include/exec/memory_ldst_phys.h.inc
b/include/exec/memory_ldst_phys.h.inc
index b9dd53c389..4033795add 100644
--- a/include/exec/memory_ldst_phys.h.inc
+++ b/include/exec/memory_ldst_phys.h.inc
@@ -20,6 +20,12 @@
*/
#ifdef TARGET_ENDIANNESS
+static inline uint32_t glue(lduw_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
+{
+ return glue(address_space_lduw, SUFFIX)(ARG1, addr,
+ MEMTXATTRS_UNSPECIFIED, NULL);
+}
+
static inline uint32_t glue(ldl_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
{
return glue(address_space_ldl, SUFFIX)(ARG1, addr,
@@ -32,10 +38,10 @@ static inline uint64_t glue(ldq_phys, SUFFIX)(ARG1_DECL,
hwaddr addr)
MEMTXATTRS_UNSPECIFIED, NULL);
}
-static inline uint32_t glue(lduw_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
+static inline void glue(stw_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
{
- return glue(address_space_lduw, SUFFIX)(ARG1, addr,
- MEMTXATTRS_UNSPECIFIED, NULL);
+ glue(address_space_stw, SUFFIX)(ARG1, addr, val,
+ MEMTXATTRS_UNSPECIFIED, NULL);
}
static inline void glue(stl_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
@@ -44,18 +50,30 @@ static inline void glue(stl_phys, SUFFIX)(ARG1_DECL, hwaddr
addr, uint32_t val)
MEMTXATTRS_UNSPECIFIED, NULL);
}
-static inline void glue(stw_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
-{
- glue(address_space_stw, SUFFIX)(ARG1, addr, val,
- MEMTXATTRS_UNSPECIFIED, NULL);
-}
-
static inline void glue(stq_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val)
{
glue(address_space_stq, SUFFIX)(ARG1, addr, val,
MEMTXATTRS_UNSPECIFIED, NULL);
}
#else
+static inline uint32_t glue(ldub_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
+{
+ return glue(address_space_ldub, SUFFIX)(ARG1, addr,
+ MEMTXATTRS_UNSPECIFIED, NULL);
+}
+
+static inline uint32_t glue(lduw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
+{
+ return glue(address_space_lduw_le, SUFFIX)(ARG1, addr,
+ MEMTXATTRS_UNSPECIFIED, NULL);
+}
+
+static inline uint32_t glue(lduw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
+{
+ return glue(address_space_lduw_be, SUFFIX)(ARG1, addr,
+ MEMTXATTRS_UNSPECIFIED, NULL);
+}
+
static inline uint32_t glue(ldl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
{
return glue(address_space_ldl_le, SUFFIX)(ARG1, addr,
@@ -80,36 +98,6 @@ static inline uint64_t glue(ldq_be_phys, SUFFIX)(ARG1_DECL,
hwaddr addr)
MEMTXATTRS_UNSPECIFIED, NULL);
}
-static inline uint32_t glue(ldub_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
-{
- return glue(address_space_ldub, SUFFIX)(ARG1, addr,
- MEMTXATTRS_UNSPECIFIED, NULL);
-}
-
-static inline uint32_t glue(lduw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
-{
- return glue(address_space_lduw_le, SUFFIX)(ARG1, addr,
- MEMTXATTRS_UNSPECIFIED, NULL);
-}
-
-static inline uint32_t glue(lduw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
-{
- return glue(address_space_lduw_be, SUFFIX)(ARG1, addr,
- MEMTXATTRS_UNSPECIFIED, NULL);
-}
-
-static inline void glue(stl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t
val)
-{
- glue(address_space_stl_le, SUFFIX)(ARG1, addr, val,
- MEMTXATTRS_UNSPECIFIED, NULL);
-}
-
-static inline void glue(stl_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t
val)
-{
- glue(address_space_stl_be, SUFFIX)(ARG1, addr, val,
- MEMTXATTRS_UNSPECIFIED, NULL);
-}
-
static inline void glue(stb_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
{
glue(address_space_stb, SUFFIX)(ARG1, addr, val,
@@ -128,6 +116,18 @@ static inline void glue(stw_be_phys, SUFFIX)(ARG1_DECL,
hwaddr addr, uint32_t va
MEMTXATTRS_UNSPECIFIED, NULL);
}
+static inline void glue(stl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t
val)
+{
+ glue(address_space_stl_le, SUFFIX)(ARG1, addr, val,
+ MEMTXATTRS_UNSPECIFIED, NULL);
+}
+
+static inline void glue(stl_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t
val)
+{
+ glue(address_space_stl_be, SUFFIX)(ARG1, addr, val,
+ MEMTXATTRS_UNSPECIFIED, NULL);
+}
+
static inline void glue(stq_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t
val)
{
glue(address_space_stq_le, SUFFIX)(ARG1, addr, val,
--
2.25.1
- [PULL 00/31] tcg patch queue, Richard Henderson, 2021/05/26
- [PULL 03/31] exec/memory_ldst: Use correct type sizes, Richard Henderson, 2021/05/26
- [PULL 01/31] exec/memory_ldst_cached: Sort declarations, Richard Henderson, 2021/05/26
- [PULL 14/31] cpu: Introduce cpu_virtio_is_big_endian(), Richard Henderson, 2021/05/26
- [PULL 11/31] cpu: Remove duplicated 'sysemu/hw_accel.h' header, Richard Henderson, 2021/05/26
- [PULL 16/31] cpu: Directly use get_paging_enabled() fallback handlers in place, Richard Henderson, 2021/05/26
- [PULL 07/31] accel/tcg: Reduce 'exec/tb-context.h' inclusion, Richard Henderson, 2021/05/26
- [PULL 02/31] exec/memory_ldst_phys: Sort declarations,
Richard Henderson <=
- [PULL 06/31] exec/memory: Use correct type size, Richard Henderson, 2021/05/26
- [PULL 05/31] exec/memory_ldst_cached: Use correct type size, Richard Henderson, 2021/05/26
- [PULL 09/31] replay: fix watchpoint processing for reverse debugging, Richard Henderson, 2021/05/26
- [PULL 10/31] tcg/aarch64: Fix tcg_out_rotl, Richard Henderson, 2021/05/26
- [PULL 08/31] accel/tcg: Keep TranslationBlock headers local to TCG, Richard Henderson, 2021/05/26
- [PULL 13/31] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs, Richard Henderson, 2021/05/26
- [PULL 12/31] cpu: Split as cpu-common / cpu-sysemu, Richard Henderson, 2021/05/26
- [PULL 04/31] exec/memory_ldst_phys: Use correct type sizes, Richard Henderson, 2021/05/26
- [PULL 15/31] cpu: Directly use cpu_write_elf*() fallback handlers in place, Richard Henderson, 2021/05/26
- [PULL 20/31] cpu: Move AVR target vmsd field from CPUClass to DeviceClass, Richard Henderson, 2021/05/26