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[PULL 014/114] accel/tcg: Add tlb_flush_range_by_mmuidx()
From: |
Peter Maydell |
Subject: |
[PULL 014/114] accel/tcg: Add tlb_flush_range_by_mmuidx() |
Date: |
Tue, 25 May 2021 16:01:44 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Forward tlb_flush_page_bits_by_mmuidx to tlb_flush_range_by_mmuidx
passing TARGET_PAGE_SIZE.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210509151618.2331764-5-f4bug@amsat.org
Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/exec/exec-all.h | 19 +++++++++++++++++++
accel/tcg/cputlb.c | 20 +++++++++++++++-----
2 files changed, 34 insertions(+), 5 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 6b036cae8f6..5a5f6d4c1a8 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -262,6 +262,20 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu,
target_ulong addr,
void tlb_flush_page_bits_by_mmuidx_all_cpus_synced
(CPUState *cpu, target_ulong addr, uint16_t idxmap, unsigned bits);
+/**
+ * tlb_flush_range_by_mmuidx
+ * @cpu: CPU whose TLB should be flushed
+ * @addr: virtual address of the start of the range to be flushed
+ * @len: length of range to be flushed
+ * @idxmap: bitmap of mmu indexes to flush
+ * @bits: number of significant bits in address
+ *
+ * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len),
+ * comparing only the low @bits worth of each virtual page.
+ */
+void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr,
+ target_ulong len, uint16_t idxmap,
+ unsigned bits);
/**
* tlb_set_page_with_attrs:
* @cpu: CPU to add this TLB entry for
@@ -365,6 +379,11 @@ tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState
*cpu, target_ulong addr,
uint16_t idxmap, unsigned bits)
{
}
+static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr,
+ target_ulong len, uint16_t idxmap,
+ unsigned bits)
+{
+}
#endif
/**
* probe_access:
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index a49a72b035e..464e7445916 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -797,13 +797,17 @@ static void
tlb_flush_page_bits_by_mmuidx_async_2(CPUState *cpu,
g_free(d);
}
-void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr,
- uint16_t idxmap, unsigned bits)
+void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr,
+ target_ulong len, uint16_t idxmap,
+ unsigned bits)
{
TLBFlushRangeData d;
- /* If all bits are significant, this devolves to tlb_flush_page. */
- if (bits >= TARGET_LONG_BITS) {
+ /*
+ * If all bits are significant, and len is small,
+ * this devolves to tlb_flush_page.
+ */
+ if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) {
tlb_flush_page_by_mmuidx(cpu, addr, idxmap);
return;
}
@@ -815,7 +819,7 @@ void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
target_ulong addr,
/* This should already be page aligned */
d.addr = addr & TARGET_PAGE_MASK;
- d.len = TARGET_PAGE_SIZE;
+ d.len = len;
d.idxmap = idxmap;
d.bits = bits;
@@ -829,6 +833,12 @@ void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
target_ulong addr,
}
}
+void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr,
+ uint16_t idxmap, unsigned bits)
+{
+ tlb_flush_range_by_mmuidx(cpu, addr, TARGET_PAGE_SIZE, idxmap, bits);
+}
+
void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu,
target_ulong addr,
uint16_t idxmap,
--
2.20.1
- [PULL 005/114] hw/arm/armsse.c: Correct modelling of SSE-300 internal SRAMs, (continued)
- [PULL 005/114] hw/arm/armsse.c: Correct modelling of SSE-300 internal SRAMs, Peter Maydell, 2021/05/25
- [PULL 007/114] hw/arm/mps2-tz: Allow board to specify a boot RAM size, Peter Maydell, 2021/05/25
- [PULL 011/114] accel/tcg: Pass length argument to tlb_flush_range_locked(), Peter Maydell, 2021/05/25
- [PULL 010/114] accel/tcg: Replace g_new() + memcpy() by g_memdup(), Peter Maydell, 2021/05/25
- [PULL 006/114] hw/arm/armsse: Convert armsse_realize() to use ERRP_GUARD, Peter Maydell, 2021/05/25
- [PULL 017/114] accel/tcg: Rename tlb_flush_page_bits -> range]_by_mmuidx_async_0, Peter Maydell, 2021/05/25
- [PULL 012/114] accel/tlb: Rename TLBFlushPageBitsByMMUIdxData -> TLBFlushRangeData, Peter Maydell, 2021/05/25
- [PULL 013/114] accel/tcg: Remove {encode,decode}_pbm_to_runon, Peter Maydell, 2021/05/25
- [PULL 016/114] accel/tlb: Add tlb_flush_range_by_mmuidx_all_cpus_synced(), Peter Maydell, 2021/05/25
- [PULL 018/114] accel/tlb: Rename tlb_flush_[page_bits > range]_by_mmuidx_async_[2 > 1], Peter Maydell, 2021/05/25
- [PULL 014/114] accel/tcg: Add tlb_flush_range_by_mmuidx(),
Peter Maydell <=
- [PULL 015/114] accel/tcg: Add tlb_flush_range_by_mmuidx_all_cpus(), Peter Maydell, 2021/05/25
- [PULL 020/114] target/arm: Add support for FEAT_TLBIOS, Peter Maydell, 2021/05/25
- [PULL 021/114] target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type, Peter Maydell, 2021/05/25
- [PULL 019/114] target/arm: Add support for FEAT_TLBIRANGE, Peter Maydell, 2021/05/25
- [PULL 023/114] target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2, Peter Maydell, 2021/05/25
- [PULL 024/114] target/arm: Implement SVE2 Integer Multiply - Unpredicated, Peter Maydell, 2021/05/25
- [PULL 022/114] disas/libvixl: Protect C system header for C++ compiler, Peter Maydell, 2021/05/25
- [PULL 025/114] target/arm: Implement SVE2 integer pairwise add and accumulate long, Peter Maydell, 2021/05/25
- [PULL 026/114] target/arm: Implement SVE2 integer unary operations (predicated), Peter Maydell, 2021/05/25
- [PULL 028/114] target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated), Peter Maydell, 2021/05/25