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[PULL 007/114] hw/arm/mps2-tz: Allow board to specify a boot RAM size
From: |
Peter Maydell |
Subject: |
[PULL 007/114] hw/arm/mps2-tz: Allow board to specify a boot RAM size |
Date: |
Tue, 25 May 2021 16:01:37 +0100 |
Currently we model the ITCM in the AN547's RAMInfo list. This is incorrect
because this RAM is really a part of the SSE-300. We can't just delete
it from the RAMInfo list, though, because this would make boot_ram_size()
assert because it wouldn't be able to find an entry in the list covering
guest address 0.
Allow a board to specify a boot RAM size manually if it doesn't have
any RAM itself at address 0 and is relying on the SSE for that, and
set the correct value for the AN547. The other boards can continue
to use the "look it up from the RAMInfo list" logic.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210510190844.17799-6-peter.maydell@linaro.org
---
hw/arm/mps2-tz.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index f2595b1c7f7..8d921afec14 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -126,6 +126,7 @@ struct MPS2TZMachineClass {
uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */
const RAMInfo *raminfo;
const char *armsse_type;
+ uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo
*/
};
struct MPS2TZMachineState {
@@ -761,6 +762,14 @@ static uint32_t boot_ram_size(MPS2TZMachineState *mms)
const RAMInfo *p;
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
+ /*
+ * Use a per-board specification (for when the boot RAM is in
+ * the SSE and so doesn't have a RAMInfo list entry)
+ */
+ if (mmc->boot_ram_size) {
+ return mmc->boot_ram_size;
+ }
+
for (p = mmc->raminfo; p->name; p++) {
if (p->base == boot_mem_base(mms)) {
return p->size;
@@ -1268,6 +1277,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, void
*data)
mmc->sram_addr_width = 15;
mmc->raminfo = an505_raminfo;
mmc->armsse_type = TYPE_IOTKIT;
+ mmc->boot_ram_size = 0;
mps2tz_set_default_ram_info(mmc);
}
@@ -1296,6 +1306,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void
*data)
mmc->sram_addr_width = 15;
mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */
mmc->armsse_type = TYPE_SSE200;
+ mmc->boot_ram_size = 0;
mps2tz_set_default_ram_info(mmc);
}
@@ -1324,6 +1335,7 @@ static void mps3tz_an524_class_init(ObjectClass *oc, void
*data)
mmc->sram_addr_width = 15;
mmc->raminfo = an524_raminfo;
mmc->armsse_type = TYPE_SSE200;
+ mmc->boot_ram_size = 0;
mps2tz_set_default_ram_info(mmc);
object_class_property_add_str(oc, "remap", mps2_get_remap, mps2_set_remap);
@@ -1357,6 +1369,7 @@ static void mps3tz_an547_class_init(ObjectClass *oc, void
*data)
mmc->sram_addr_width = 21;
mmc->raminfo = an547_raminfo;
mmc->armsse_type = TYPE_SSE300;
+ mmc->boot_ram_size = 512 * KiB;
mps2tz_set_default_ram_info(mmc);
}
--
2.20.1
- [PULL 000/114] target-arm queue, Peter Maydell, 2021/05/25
- [PULL 001/114] hw/arm/smmuv3: Another range invalidation fix, Peter Maydell, 2021/05/25
- [PULL 003/114] hw/arm/mps2-tz: Don't duplicate modelling of SRAM in AN524, Peter Maydell, 2021/05/25
- [PULL 002/114] hw/intc/arm_gicv3_cpuif: Fix EOIR write access check logic, Peter Maydell, 2021/05/25
- [PULL 004/114] hw/arm/mps2-tz: Make SRAM_ADDR_WIDTH board-specific, Peter Maydell, 2021/05/25
- [PULL 009/114] target/arm: Use correct SP in M-profile exception return, Peter Maydell, 2021/05/25
- [PULL 008/114] hw/arm: Model TCMs in the SSE-300, not the AN547, Peter Maydell, 2021/05/25
- [PULL 005/114] hw/arm/armsse.c: Correct modelling of SSE-300 internal SRAMs, Peter Maydell, 2021/05/25
- [PULL 007/114] hw/arm/mps2-tz: Allow board to specify a boot RAM size,
Peter Maydell <=
- [PULL 011/114] accel/tcg: Pass length argument to tlb_flush_range_locked(), Peter Maydell, 2021/05/25
- [PULL 010/114] accel/tcg: Replace g_new() + memcpy() by g_memdup(), Peter Maydell, 2021/05/25
- [PULL 006/114] hw/arm/armsse: Convert armsse_realize() to use ERRP_GUARD, Peter Maydell, 2021/05/25
- [PULL 017/114] accel/tcg: Rename tlb_flush_page_bits -> range]_by_mmuidx_async_0, Peter Maydell, 2021/05/25
- [PULL 012/114] accel/tlb: Rename TLBFlushPageBitsByMMUIdxData -> TLBFlushRangeData, Peter Maydell, 2021/05/25
- [PULL 013/114] accel/tcg: Remove {encode,decode}_pbm_to_runon, Peter Maydell, 2021/05/25
- [PULL 016/114] accel/tlb: Add tlb_flush_range_by_mmuidx_all_cpus_synced(), Peter Maydell, 2021/05/25
- [PULL 018/114] accel/tlb: Rename tlb_flush_[page_bits > range]_by_mmuidx_async_[2 > 1], Peter Maydell, 2021/05/25
- [PULL 014/114] accel/tcg: Add tlb_flush_range_by_mmuidx(), Peter Maydell, 2021/05/25
- [PULL 015/114] accel/tcg: Add tlb_flush_range_by_mmuidx_all_cpus(), Peter Maydell, 2021/05/25