Re: [PATCH 0/9] target/arm: MVE preliminaries

[no-reply]

Patchew URL: 
20210520152840.24453-1-peter.maydell@linaro.org/">https://patchew.org/QEMU/20210520152840.24453-1-peter.maydell@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20210520152840.24453-1-peter.maydell@linaro.org
Subject: [PATCH 0/9] target/arm: MVE preliminaries

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]         patchew/20210520152840.24453-1-peter.maydell@linaro.org -> 
patchew/20210520152840.24453-1-peter.maydell@linaro.org
 * [new tag]         patchew/20210520153831.11873-1-alex.bennee@linaro.org -> 
patchew/20210520153831.11873-1-alex.bennee@linaro.org
Switched to a new branch 'test'
5714b29 target/arm: Allow board models to specify initial NS VTOR
0a91c4d target/arm: Enable FPSCR.QC bit for MVE
d47da78 target/arm: Make FPSCR.LTPSIZE writable for MVE
6c7229a target/arm: Implement M-profile VPR register
47dbed2 target/arm: Fix return values in fp_sysreg_checks()
4b36a72 target/arm: Add MVE check to VMOV_reg_sp and VMOV_reg_dp
dbefafd target/arm: Move fpsp/fpdp isar check into callers of do_vfp_2op_sp/dp
493a859 target/arm: Update feature checks for insns which are "MVE or FP"
633fa0c target/arm: Add isar feature check functions for MVE

=== OUTPUT BEGIN ===
1/9 Checking commit 633fa0c8de0b (target/arm: Add isar feature check functions 
for MVE)
2/9 Checking commit 493a859c1d72 (target/arm: Update feature checks for insns 
which are "MVE or FP")
3/9 Checking commit dbefafdfeff3 (target/arm: Move fpsp/fpdp isar check into 
callers of do_vfp_2op_sp/dp)
4/9 Checking commit 4b36a72b4fd7 (target/arm: Add MVE check to VMOV_reg_sp and 
VMOV_reg_dp)
ERROR: spaces required around that '*' (ctx:WxV)
#28: FILE: target/arm/translate-vfp.c:2823:
+                                      arg_##INSN##_##PREC *a)   \
                                                           ^

total: 1 errors, 0 warnings, 21 lines checked

Patch 4/9 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

5/9 Checking commit 47dbed22cf5a (target/arm: Fix return values in 
fp_sysreg_checks())
6/9 Checking commit 6c7229aab445 (target/arm: Implement M-profile VPR register)
7/9 Checking commit d47da78456e0 (target/arm: Make FPSCR.LTPSIZE writable for 
MVE)
8/9 Checking commit 0a91c4deb285 (target/arm: Enable FPSCR.QC bit for MVE)
9/9 Checking commit 5714b29a3b6e (target/arm: Allow board models to specify 
initial NS VTOR)
WARNING: line over 80 characters
#55: FILE: include/hw/arm/armv7m.h:49:
+ * + Property "init-nsvtor": non-secure VTOR reset value (forwarded to CPU 
object)

total: 0 errors, 1 warnings, 63 lines checked

Patch 9/9 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
20210520152840.24453-1-peter.maydell@linaro.org/testing.checkpatch/?type=message">http://patchew.org/logs/20210520152840.24453-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
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