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Re: [PATCH 8/9] target/arm: Enable FPSCR.QC bit for MVE
From: |
Peter Maydell |
Subject: |
Re: [PATCH 8/9] target/arm: Enable FPSCR.QC bit for MVE |
Date: |
Mon, 24 May 2021 18:08:12 +0100 |
On Mon, 24 May 2021 at 17:59, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 5/20/21 8:28 AM, Peter Maydell wrote:
> > MVE has an FPSCR.QC bit similar to the A-profile Neon one;
> > when MVE is implemented make the bit writeable.
> >
> > Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> > ---
> > target/arm/vfp_helper.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
There's a followon bit to this patch which I didn't notice
at first, which is that the handling of ARM_VFP_FPSCR_NZCVQC
in the "fp_sysreg" code also needs to be updated to read/write
the QC bit (currently it has TODO comments about this.)
Given that this patch is currently a one-liner I think I'll
just respin it as a single patch with all the accesses to QC fixed.
thanks
-- PMM
- [PATCH 3/9] target/arm: Move fpsp/fpdp isar check into callers of do_vfp_2op_sp/dp, (continued)
- [PATCH 3/9] target/arm: Move fpsp/fpdp isar check into callers of do_vfp_2op_sp/dp, Peter Maydell, 2021/05/20
- [PATCH 7/9] target/arm: Make FPSCR.LTPSIZE writable for MVE, Peter Maydell, 2021/05/20
- [PATCH 5/9] target/arm: Fix return values in fp_sysreg_checks(), Peter Maydell, 2021/05/20
- [PATCH 9/9] target/arm: Allow board models to specify initial NS VTOR, Peter Maydell, 2021/05/20
- [PATCH 8/9] target/arm: Enable FPSCR.QC bit for MVE, Peter Maydell, 2021/05/20
- Re: [PATCH 0/9] target/arm: MVE preliminaries, no-reply, 2021/05/20