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[PULL 31/46] target/ppc: Fix POWER9 radix guest HV interrupt AIL behavio
From: |
David Gibson |
Subject: |
[PULL 31/46] target/ppc: Fix POWER9 radix guest HV interrupt AIL behaviour |
Date: |
Tue, 4 May 2021 15:52:57 +1000 |
From: Nicholas Piggin <npiggin@gmail.com>
ISA v3.0 radix guest execution has a quirk in AIL behaviour such that
the LPCR[AIL] value can apply to hypervisor interrupts.
This affects machines that emulate HV=1 mode (i.e., powernv9).
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20210415054227.1793812-2-npiggin@gmail.com>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/excp_helper.c | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 5c95e0c103..344af66f66 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -791,14 +791,23 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
#endif
/*
- * AIL only works if there is no HV transition and we are running
- * with translations enabled
+ * AIL only works if MSR[IR] and MSR[DR] are both enabled.
*/
- if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1) ||
- ((new_msr & MSR_HVB) && !(msr & MSR_HVB))) {
+ if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1)) {
ail = 0;
}
+ /*
+ * AIL does not work if there is a MSR[HV] 0->1 transition and the
+ * partition is in HPT mode. For radix guests, such interrupts are
+ * allowed to be delivered to the hypervisor in ail mode.
+ */
+ if ((new_msr & MSR_HVB) && !(msr & MSR_HVB)) {
+ if (!(env->spr[SPR_LPCR] & LPCR_HR)) {
+ ail = 0;
+ }
+ }
+
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
cpu_abort(cs, "Raised an exception without defined vector %d\n",
--
2.31.1
- [PULL 20/46] vt82c686: QOM-ify superio related functionality, (continued)
- [PULL 20/46] vt82c686: QOM-ify superio related functionality, David Gibson, 2021/05/04
- [PULL 17/46] target/ppc: Remove env->immu_idx and env->dmmu_idx, David Gibson, 2021/05/04
- [PULL 25/46] hw/ppc: Add emulation of Genesi/bPlan Pegasos II, David Gibson, 2021/05/04
- [PULL 24/46] hw/pci-host: Add emulation of Marvell MV64361 PPC system controller, David Gibson, 2021/05/04
- [PULL 13/46] target/ppc: Put dbcr0 single-step bits into hflags, David Gibson, 2021/05/04
- [PULL 19/46] target/ppc: Validate hflags with CONFIG_DEBUG_TCG, David Gibson, 2021/05/04
- [PULL 21/46] vt82c686: Add VT8231_SUPERIO based on VIA_SUPERIO, David Gibson, 2021/05/04
- [PULL 22/46] vt82c686: Introduce abstract TYPE_VIA_ISA and base vt82c686b_isa on it, David Gibson, 2021/05/04
- [PULL 23/46] vt82c686: Add emulation of VT8231 south bridge, David Gibson, 2021/05/04
- [PULL 28/46] roms/Makefile: Update ppce500 u-boot build directory name, David Gibson, 2021/05/04
- [PULL 31/46] target/ppc: Fix POWER9 radix guest HV interrupt AIL behaviour,
David Gibson <=
- [PULL 26/46] spapr: Rename RTAS_MAX_ADDR to FDT_MAX_ADDR, David Gibson, 2021/05/04
- [PULL 33/46] ppc: Rename current DAWR macros and variables, David Gibson, 2021/05/04
- [PULL 27/46] ppc/spapr: Add support for implement support for H_SCM_HEALTH, David Gibson, 2021/05/04
- [PULL 34/46] spapr.c: do not use MachineClass::max_cpus to limit CPUs, David Gibson, 2021/05/04
- [PULL 30/46] docs/system: ppc: Add documentation for ppce500 machine, David Gibson, 2021/05/04
- [PULL 29/46] roms/u-boot: Bump ppce500 u-boot to v2021.04 to fix broken pci support, David Gibson, 2021/05/04
- [PULL 32/46] target/ppc: POWER10 supports scv, David Gibson, 2021/05/04
- [PULL 36/46] spapr_drc.c: handle hotunplug errors in drc_unisolate_logical(), David Gibson, 2021/05/04
- [PULL 35/46] spapr.h: increase FDT_MAX_SIZE, David Gibson, 2021/05/04
- [PULL 37/46] target/ppc: code motion from translate_init.c.inc to gdbstub.c, David Gibson, 2021/05/04