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[PULL 21/46] vt82c686: Add VT8231_SUPERIO based on VIA_SUPERIO
From: |
David Gibson |
Subject: |
[PULL 21/46] vt82c686: Add VT8231_SUPERIO based on VIA_SUPERIO |
Date: |
Tue, 4 May 2021 15:52:47 +1000 |
From: BALATON Zoltan <balaton@eik.bme.hu>
The VT8231 south bridge is very similar to VT82C686B but there are
some differences in register addresses and functionality, e.g. the
VT8231 only has one serial port. This commit adds VT8231_SUPERIO
subclass based on the abstract VIA_SUPERIO class to emulate the
superio part of VT8231.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<8108809321f9ecf3fb1aea22ddaeccc7c3a57c8e.1616680239.git.balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/isa/vt82c686.c | 102 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 102 insertions(+)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index ea55117724..952c6fc867 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -433,6 +433,107 @@ static const TypeInfo vt82c686b_superio_info = {
};
+#define TYPE_VT8231_SUPERIO "vt8231-superio"
+
+static void vt8231_superio_cfg_write(void *opaque, hwaddr addr,
+ uint64_t data, unsigned size)
+{
+ ViaSuperIOState *sc = opaque;
+ uint8_t idx = sc->regs[0];
+
+ if (addr == 0) { /* config index register */
+ sc->regs[0] = data;
+ return;
+ }
+
+ /* config data register */
+ trace_via_superio_write(idx, data);
+ switch (idx) {
+ case 0x00 ... 0xdf:
+ case 0xe7 ... 0xef:
+ case 0xf0 ... 0xf1:
+ case 0xf5:
+ case 0xf8:
+ case 0xfd:
+ /* ignore write to read only registers */
+ return;
+ default:
+ qemu_log_mask(LOG_UNIMP,
+ "via_superio_cfg: unimplemented register 0x%x\n", idx);
+ break;
+ }
+ sc->regs[idx] = data;
+}
+
+static const MemoryRegionOps vt8231_superio_cfg_ops = {
+ .read = via_superio_cfg_read,
+ .write = vt8231_superio_cfg_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
+
+static void vt8231_superio_reset(DeviceState *dev)
+{
+ ViaSuperIOState *s = VIA_SUPERIO(dev);
+
+ memset(s->regs, 0, sizeof(s->regs));
+ /* Device ID */
+ s->regs[0xf0] = 0x3c;
+ /* Device revision */
+ s->regs[0xf1] = 0x01;
+ /* Function select - all disabled */
+ vt8231_superio_cfg_write(s, 0, 0xf2, 1);
+ vt8231_superio_cfg_write(s, 1, 0x03, 1);
+ /* Serial port base addr */
+ vt8231_superio_cfg_write(s, 0, 0xf4, 1);
+ vt8231_superio_cfg_write(s, 1, 0xfe, 1);
+ /* Parallel port base addr */
+ vt8231_superio_cfg_write(s, 0, 0xf6, 1);
+ vt8231_superio_cfg_write(s, 1, 0xde, 1);
+ /* Floppy ctrl base addr */
+ vt8231_superio_cfg_write(s, 0, 0xf7, 1);
+ vt8231_superio_cfg_write(s, 1, 0xfc, 1);
+
+ vt8231_superio_cfg_write(s, 0, 0, 1);
+}
+
+static void vt8231_superio_init(Object *obj)
+{
+ VIA_SUPERIO(obj)->io_ops = &vt8231_superio_cfg_ops;
+}
+
+static uint16_t vt8231_superio_serial_iobase(ISASuperIODevice *sio,
+ uint8_t index)
+{
+ return 0x2f8; /* FIXME: This should be settable via registers f2-f4 */
+}
+
+static void vt8231_superio_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
+
+ dc->reset = vt8231_superio_reset;
+ sc->serial.count = 1;
+ sc->serial.get_iobase = vt8231_superio_serial_iobase;
+ sc->parallel.count = 1;
+ sc->ide.count = 0; /* emulated by via-ide */
+ sc->floppy.count = 1;
+}
+
+static const TypeInfo vt8231_superio_info = {
+ .name = TYPE_VT8231_SUPERIO,
+ .parent = TYPE_VIA_SUPERIO,
+ .instance_size = sizeof(ViaSuperIOState),
+ .instance_init = vt8231_superio_init,
+ .class_size = sizeof(ISASuperIOClass),
+ .class_init = vt8231_superio_class_init,
+};
+
+
OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA)
struct VT82C686BISAState {
@@ -556,6 +657,7 @@ static void vt82c686b_register_types(void)
type_register_static(&vt8231_pm_info);
type_register_static(&via_superio_info);
type_register_static(&vt82c686b_superio_info);
+ type_register_static(&vt8231_superio_info);
type_register_static(&via_info);
}
--
2.31.1
- [PULL 14/46] target/ppc: Create helper_scv, (continued)
- [PULL 14/46] target/ppc: Create helper_scv, David Gibson, 2021/05/04
- [PULL 15/46] target/ppc: Put LPCR[GTSE] in hflags, David Gibson, 2021/05/04
- [PULL 16/46] target/ppc: Remove MSR_SA and MSR_AP from hflags, David Gibson, 2021/05/04
- [PULL 18/46] linux-user/ppc: Fix msr updates for signal handling, David Gibson, 2021/05/04
- [PULL 20/46] vt82c686: QOM-ify superio related functionality, David Gibson, 2021/05/04
- [PULL 17/46] target/ppc: Remove env->immu_idx and env->dmmu_idx, David Gibson, 2021/05/04
- [PULL 25/46] hw/ppc: Add emulation of Genesi/bPlan Pegasos II, David Gibson, 2021/05/04
- [PULL 24/46] hw/pci-host: Add emulation of Marvell MV64361 PPC system controller, David Gibson, 2021/05/04
- [PULL 13/46] target/ppc: Put dbcr0 single-step bits into hflags, David Gibson, 2021/05/04
- [PULL 19/46] target/ppc: Validate hflags with CONFIG_DEBUG_TCG, David Gibson, 2021/05/04
- [PULL 21/46] vt82c686: Add VT8231_SUPERIO based on VIA_SUPERIO,
David Gibson <=
- [PULL 22/46] vt82c686: Introduce abstract TYPE_VIA_ISA and base vt82c686b_isa on it, David Gibson, 2021/05/04
- [PULL 23/46] vt82c686: Add emulation of VT8231 south bridge, David Gibson, 2021/05/04
- [PULL 28/46] roms/Makefile: Update ppce500 u-boot build directory name, David Gibson, 2021/05/04
- [PULL 31/46] target/ppc: Fix POWER9 radix guest HV interrupt AIL behaviour, David Gibson, 2021/05/04
- [PULL 26/46] spapr: Rename RTAS_MAX_ADDR to FDT_MAX_ADDR, David Gibson, 2021/05/04
- [PULL 33/46] ppc: Rename current DAWR macros and variables, David Gibson, 2021/05/04
- [PULL 27/46] ppc/spapr: Add support for implement support for H_SCM_HEALTH, David Gibson, 2021/05/04
- [PULL 34/46] spapr.c: do not use MachineClass::max_cpus to limit CPUs, David Gibson, 2021/05/04
- [PULL 30/46] docs/system: ppc: Add documentation for ppce500 machine, David Gibson, 2021/05/04
- [PULL 29/46] roms/u-boot: Bump ppce500 u-boot to v2021.04 to fix broken pci support, David Gibson, 2021/05/04