[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 08/42] hw/riscv: Connect Shakti UART to Shakti platform
From: |
Alistair Francis |
Subject: |
[PULL 08/42] hw/riscv: Connect Shakti UART to Shakti platform |
Date: |
Tue, 4 May 2021 08:12:53 +1000 |
From: Vijai Kumar K <vijai@behindbytes.com>
Connect one shakti uart to the shakti_c machine.
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-5-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/shakti_c.h | 2 ++
hw/riscv/shakti_c.c | 8 ++++++++
2 files changed, 10 insertions(+)
diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
index 8ffc2b0213..50a2b79086 100644
--- a/include/hw/riscv/shakti_c.h
+++ b/include/hw/riscv/shakti_c.h
@@ -21,6 +21,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/boards.h"
+#include "hw/char/shakti_uart.h"
#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
#define RISCV_SHAKTI_SOC(obj) \
@@ -33,6 +34,7 @@ typedef struct ShaktiCSoCState {
/*< public >*/
RISCVHartArrayState cpus;
DeviceState *plic;
+ ShaktiUartState uart;
MemoryRegion rom;
} ShaktiCSoCState;
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index c8205d3f22..e207fa83dd 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -125,6 +125,13 @@ static void shakti_c_soc_state_realize(DeviceState *dev,
Error **errp)
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
SIFIVE_CLINT_TIMEBASE_FREQ, false);
+ qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0));
+ if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0,
+ shakti_c_memmap[SHAKTI_C_UART].base);
+
/* ROM */
memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
@@ -143,6 +150,7 @@ static void shakti_c_soc_instance_init(Object *obj)
ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
+ object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART);
/*
* CPU type is fixed and we are not supporting passing from commandline
yet.
--
2.31.1
- [PULL 00/42] riscv-to-apply queue, Alistair Francis, 2021/05/03
- [PULL 02/42] docs/system/generic-loader.rst: Fix style, Alistair Francis, 2021/05/03
- [PULL 06/42] riscv: Add initial support for Shakti C machine, Alistair Francis, 2021/05/03
- [PULL 07/42] hw/char: Add Shakti UART emulation, Alistair Francis, 2021/05/03
- [PULL 05/42] target/riscv: Add Shakti C class CPU, Alistair Francis, 2021/05/03
- [PULL 01/42] target/riscv: Remove privilege v1.9 specific CSR related code, Alistair Francis, 2021/05/03
- [PULL 03/42] target/riscv: Align the data type of reset vector address, Alistair Francis, 2021/05/03
- [PULL 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[], Alistair Francis, 2021/05/03
- [PULL 08/42] hw/riscv: Connect Shakti UART to Shakti platform,
Alistair Francis <=
- [PULL 09/42] target/riscv: Convert the RISC-V exceptions to an enum, Alistair Francis, 2021/05/03
- [PULL 10/42] target/riscv: Use the RISCVException enum for CSR predicates, Alistair Francis, 2021/05/03
- [PULL 13/42] target/riscv: Use RISCVException enum for CSR access, Alistair Francis, 2021/05/03
- [PULL 12/42] target/riscv: Use the RISCVException enum for CSR operations, Alistair Francis, 2021/05/03
- [PULL 11/42] target/riscv: Fix 32-bit HS mode access permissions, Alistair Francis, 2021/05/03
- [PULL 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers, Alistair Francis, 2021/05/03
- [PULL 15/42] hw/opentitan: Update the interrupt layout, Alistair Francis, 2021/05/03
- [PULL 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine, Alistair Francis, 2021/05/03
- [PULL 17/42] riscv: don't look at SUM when accessing memory from a debugger context, Alistair Francis, 2021/05/03
- [PULL 18/42] target/riscv: Fixup saturate subtract function, Alistair Francis, 2021/05/03