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[PULL 03/42] target/riscv: Align the data type of reset vector address
From: |
Alistair Francis |
Subject: |
[PULL 03/42] target/riscv: Align the data type of reset vector address |
Date: |
Tue, 4 May 2021 08:12:48 +1000 |
From: Dylan Jhong <dylan@andestech.com>
Use target_ulong to instead of uint64_t on reset vector address
to adapt on both 32/64 machine.
Signed-off-by: Dylan Jhong <dylan@andestech.com>
Signed-off-by: Ruinland ChuanTzu Tsai <ruinland@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210329034801.22667-1-dylan@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 86e7dbeb20..047d6344fe 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -137,7 +137,7 @@ static void set_feature(CPURISCVState *env, int feature)
env->features |= (1ULL << feature);
}
-static void set_resetvec(CPURISCVState *env, int resetvec)
+static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
{
#ifndef CONFIG_USER_ONLY
env->resetvec = resetvec;
--
2.31.1
- [PULL 00/42] riscv-to-apply queue, Alistair Francis, 2021/05/03
- [PULL 02/42] docs/system/generic-loader.rst: Fix style, Alistair Francis, 2021/05/03
- [PULL 06/42] riscv: Add initial support for Shakti C machine, Alistair Francis, 2021/05/03
- [PULL 07/42] hw/char: Add Shakti UART emulation, Alistair Francis, 2021/05/03
- [PULL 05/42] target/riscv: Add Shakti C class CPU, Alistair Francis, 2021/05/03
- [PULL 01/42] target/riscv: Remove privilege v1.9 specific CSR related code, Alistair Francis, 2021/05/03
- [PULL 03/42] target/riscv: Align the data type of reset vector address,
Alistair Francis <=
- [PULL 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[], Alistair Francis, 2021/05/03
- [PULL 08/42] hw/riscv: Connect Shakti UART to Shakti platform, Alistair Francis, 2021/05/03
- [PULL 09/42] target/riscv: Convert the RISC-V exceptions to an enum, Alistair Francis, 2021/05/03
- [PULL 10/42] target/riscv: Use the RISCVException enum for CSR predicates, Alistair Francis, 2021/05/03
- [PULL 13/42] target/riscv: Use RISCVException enum for CSR access, Alistair Francis, 2021/05/03
- [PULL 12/42] target/riscv: Use the RISCVException enum for CSR operations, Alistair Francis, 2021/05/03
- [PULL 11/42] target/riscv: Fix 32-bit HS mode access permissions, Alistair Francis, 2021/05/03
- [PULL 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers, Alistair Francis, 2021/05/03
- [PULL 15/42] hw/opentitan: Update the interrupt layout, Alistair Francis, 2021/05/03
- [PULL 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine, Alistair Francis, 2021/05/03