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[PULL 10/31] Hexagon (target/hexagon) properly generate TB end for DISAS
From: |
Richard Henderson |
Subject: |
[PULL 10/31] Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN |
Date: |
Sat, 1 May 2021 11:43:03 -0700 |
From: Taylor Simpson <tsimpson@quicinc.com>
When exiting a TB, generate all the code before returning from
hexagon_tr_translate_packet so that nothing needs to be done in
hexagon_tr_tb_stop.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-6-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hexagon/translate.h | 3 --
target/hexagon/translate.c | 62 ++++++++++++++++++++------------------
2 files changed, 33 insertions(+), 32 deletions(-)
diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index 938f7fbb9f..12506c8caf 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -86,8 +86,5 @@ extern TCGv hex_llsc_addr;
extern TCGv hex_llsc_val;
extern TCGv_i64 hex_llsc_val_i64;
-void gen_exception(int excp);
-void gen_exception_debug(void);
-
void process_store(DisasContext *ctx, Packet *pkt, int slot_num);
#endif
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index e235fdb315..9f2a531969 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -54,16 +54,40 @@ static const char * const hexagon_prednames[] = {
"p0", "p1", "p2", "p3"
};
-void gen_exception(int excp)
+static void gen_exception_raw(int excp)
{
TCGv_i32 helper_tmp = tcg_const_i32(excp);
gen_helper_raise_exception(cpu_env, helper_tmp);
tcg_temp_free_i32(helper_tmp);
}
-void gen_exception_debug(void)
+static void gen_exec_counters(DisasContext *ctx)
{
- gen_exception(EXCP_DEBUG);
+ tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT],
+ hex_gpr[HEX_REG_QEMU_PKT_CNT], ctx->num_packets);
+ tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT],
+ hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns);
+}
+
+static void gen_end_tb(DisasContext *ctx)
+{
+ gen_exec_counters(ctx);
+ tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
+ if (ctx->base.singlestep_enabled) {
+ gen_exception_raw(EXCP_DEBUG);
+ } else {
+ tcg_gen_exit_tb(NULL, 0);
+ }
+ ctx->base.is_jmp = DISAS_NORETURN;
+}
+
+static void gen_exception_end_tb(DisasContext *ctx, int excp)
+{
+ gen_exec_counters(ctx);
+ tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
+ gen_exception_raw(excp);
+ ctx->base.is_jmp = DISAS_NORETURN;
+
}
#if HEX_DEBUG
@@ -225,8 +249,7 @@ static void gen_insn(CPUHexagonState *env, DisasContext
*ctx,
mark_implicit_writes(ctx, insn);
insn->generate(env, ctx, insn, pkt);
} else {
- gen_exception(HEX_EXCP_INVALID_OPCODE);
- ctx->base.is_jmp = DISAS_NORETURN;
+ gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE);
}
}
@@ -447,14 +470,6 @@ static void update_exec_counters(DisasContext *ctx, Packet
*pkt)
ctx->num_insns += num_real_insns;
}
-static void gen_exec_counters(DisasContext *ctx)
-{
- tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT],
- hex_gpr[HEX_REG_QEMU_PKT_CNT], ctx->num_packets);
- tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT],
- hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns);
-}
-
static void gen_commit_packet(DisasContext *ctx, Packet *pkt)
{
gen_reg_writes(ctx);
@@ -478,7 +493,7 @@ static void gen_commit_packet(DisasContext *ctx, Packet
*pkt)
#endif
if (pkt->pkt_has_cof) {
- ctx->base.is_jmp = DISAS_NORETURN;
+ gen_end_tb(ctx);
}
}
@@ -491,8 +506,7 @@ static void decode_and_translate_packet(CPUHexagonState
*env, DisasContext *ctx)
nwords = read_packet_words(env, ctx, words);
if (!nwords) {
- gen_exception(HEX_EXCP_INVALID_PACKET);
- ctx->base.is_jmp = DISAS_NORETURN;
+ gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET);
return;
}
@@ -505,8 +519,7 @@ static void decode_and_translate_packet(CPUHexagonState
*env, DisasContext *ctx)
gen_commit_packet(ctx, &pkt);
ctx->base.pc_next += pkt.encod_pkt_size_in_bytes;
} else {
- gen_exception(HEX_EXCP_INVALID_PACKET);
- ctx->base.is_jmp = DISAS_NORETURN;
+ gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET);
}
}
@@ -536,9 +549,7 @@ static bool hexagon_tr_breakpoint_check(DisasContextBase
*dcbase, CPUState *cpu,
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next);
- ctx->base.is_jmp = DISAS_NORETURN;
- gen_exception_debug();
+ gen_exception_end_tb(ctx, EXCP_DEBUG);
/*
* The address covered by the breakpoint must be included in
* [tb->pc, tb->pc + tb->size) in order to for it to be
@@ -601,19 +612,12 @@ static void hexagon_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cpu)
gen_exec_counters(ctx);
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next);
if (ctx->base.singlestep_enabled) {
- gen_exception_debug();
+ gen_exception_raw(EXCP_DEBUG);
} else {
tcg_gen_exit_tb(NULL, 0);
}
break;
case DISAS_NORETURN:
- gen_exec_counters(ctx);
- tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
- if (ctx->base.singlestep_enabled) {
- gen_exception_debug();
- } else {
- tcg_gen_exit_tb(NULL, 0);
- }
break;
default:
g_assert_not_reached();
--
2.25.1
- [PULL 02/31] target/hexagon: remove unnecessary checks in find_iclass_slots, (continued)
- [PULL 02/31] target/hexagon: remove unnecessary checks in find_iclass_slots, Richard Henderson, 2021/05/01
- [PULL 04/31] target/hexagon: fix typo in comment, Richard Henderson, 2021/05/01
- [PULL 03/31] target/hexagon: Change DECODE_MAPPED_REG operand name to OPNUM, Richard Henderson, 2021/05/01
- [PULL 06/31] Hexagon (target/hexagon) TCG generation cleanup, Richard Henderson, 2021/05/01
- [PULL 08/31] Hexagon (target/hexagon) remove unnecessary inline directives, Richard Henderson, 2021/05/01
- [PULL 09/31] Hexagon (target/hexagon) use env_archcpu and env_cpu, Richard Henderson, 2021/05/01
- [PULL 11/31] Hexagon (target/hexagon) decide if pred has been written at TCG gen time, Richard Henderson, 2021/05/01
- [PULL 12/31] Hexagon (target/hexagon) change variables from int to bool when appropriate, Richard Henderson, 2021/05/01
- [PULL 16/31] Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn, Richard Henderson, 2021/05/01
- [PULL 07/31] Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair, Richard Henderson, 2021/05/01
- [PULL 10/31] Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN,
Richard Henderson <=
- [PULL 13/31] Hexagon (target/hexagon) remove unused carry_from_add64 function, Richard Henderson, 2021/05/01
- [PULL 05/31] target/hexagon: remove unnecessary semicolons, Richard Henderson, 2021/05/01
- [PULL 14/31] Hexagon (target/hexagon) change type of softfloat_roundingmodes, Richard Henderson, 2021/05/01
- [PULL 17/31] Hexagon (target/hexagon) use softfloat for float-to-int conversions, Richard Henderson, 2021/05/01
- [PULL 15/31] Hexagon (target/hexagon) use softfloat default NaN and tininess, Richard Henderson, 2021/05/01
- [PULL 18/31] Hexagon (target/hexagon) cleanup ternary operators in semantics, Richard Henderson, 2021/05/01
- [PULL 20/31] Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.h, Richard Henderson, 2021/05/01
- [PULL 26/31] Hexagon (target/hexagon) add A4_addp_c/A4_subp_c, Richard Henderson, 2021/05/01
- [PULL 19/31] Hexagon (target/hexagon) cleanup reg_field_info definition, Richard Henderson, 2021/05/01
- [PULL 24/31] Hexagon (target/hexagon) add A5_ACS (vacsh), Richard Henderson, 2021/05/01