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[PATCH v2 12/15] target/ppc: Remove MSR_SA and MSR_AP from hflags
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From: |
Richard Henderson |
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Subject: |
[PATCH v2 12/15] target/ppc: Remove MSR_SA and MSR_AP from hflags |
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Date: |
Fri, 12 Mar 2021 19:00:15 -0600 |
Nothing within the translator -- or anywhere else for that
matter -- checks MSR_SA or MSR_AP on the 602. This may be
a mistake. However, for the moment, we need not record these
bits in hflags.
This allows us to simplify HFLAGS_VSX computation by moving
it to overlap with MSR_VSX.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/cpu.h | 4 +---
target/ppc/helper_regs.c | 7 +++----
2 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 07a4331eec..23ff16c154 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -599,14 +599,12 @@ enum {
HFLAGS_DR = 4, /* MSR_DR */
HFLAGS_IR = 5, /* MSR_IR */
HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */
- HFLAGS_VSX = 7, /* from MSR_VSX if cpu has VSX; avoid overlap w/ MSR_AP */
HFLAGS_TM = 8, /* computed from MSR_TM */
HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */
HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */
HFLAGS_GTSE = 11, /* computed from SPR_LPCR[GTSE] */
HFLAGS_FP = 13, /* MSR_FP */
- HFLAGS_SA = 22, /* MSR_SA */
- HFLAGS_AP = 23, /* MSR_AP */
+ HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */
HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */
};
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 8479789e24..d62921c322 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -95,8 +95,7 @@ void hreg_compute_hflags(CPUPPCState *env)
/* Some bits come straight across from MSR. */
msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) |
- (1 << MSR_DR) | (1 << MSR_IR) |
- (1 << MSR_FP) | (1 << MSR_SA) | (1 << MSR_AP));
+ (1 << MSR_DR) | (1 << MSR_IR) | (1 << MSR_FP));
if (ppc_flags & POWERPC_FLAG_HID0_LE) {
/*
@@ -133,8 +132,8 @@ void hreg_compute_hflags(CPUPPCState *env)
if (ppc_flags & POWERPC_FLAG_VRE) {
msr_mask |= 1 << MSR_VR;
}
- if ((ppc_flags & POWERPC_FLAG_VSX) && (msr & (1 << MSR_VSX))) {
- hflags |= 1 << HFLAGS_VSX;
+ if (ppc_flags & POWERPC_FLAG_VSX) {
+ msr_mask |= 1 << MSR_VSX;
}
if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) {
hflags |= 1 << HFLAGS_TM;
--
2.25.1
- [PATCH v2 01/15] target/ppc: Move helper_regs.h functions out-of-line, (continued)
- [PATCH v2 01/15] target/ppc: Move helper_regs.h functions out-of-line, Richard Henderson, 2021/03/12
- [PATCH v2 02/15] target/ppc: Move 601 hflags adjustment to hreg_compute_hflags, Richard Henderson, 2021/03/12
- [PATCH v2 03/15] target/ppc: Properly sync cpu state with new msr in cpu_load_old, Richard Henderson, 2021/03/12
- [PATCH v2 04/15] target/ppc: Do not call hreg_compute_mem_idx after ppc_store_msr, Richard Henderson, 2021/03/12
- [PATCH v2 05/15] target/ppc: Retain hflags_nmsr only for migration, Richard Henderson, 2021/03/12
- [PATCH v2 06/15] target/ppc: Fix comment for MSR_FE{0,1}, Richard Henderson, 2021/03/12
- [PATCH v2 07/15] target/ppc: Disconnect hflags from MSR, Richard Henderson, 2021/03/12
- [PATCH v2 08/15] target/ppc: Reduce env->hflags to uint32_t, Richard Henderson, 2021/03/12
- [PATCH v2 09/15] target/ppc: Put dbcr0 single-step bits into hflags, Richard Henderson, 2021/03/12
- [PATCH v2 10/15] target/ppc: Create helper_scv, Richard Henderson, 2021/03/12
- [PATCH v2 12/15] target/ppc: Remove MSR_SA and MSR_AP from hflags,
Richard Henderson <=
- [PATCH v2 14/15] hw/ppc: Use hreg_store_msr for msr updates, Richard Henderson, 2021/03/12
- [PATCH v2 11/15] target/ppc: Put LPCR[GTSE] in hflags, Richard Henderson, 2021/03/12
- [PATCH v2 13/15] target/ppc: Remove env->immu_idx and env->dmmu_idx, Richard Henderson, 2021/03/12
- [PATCH v2 15/15] target/ppc: Validate hflags with CONFIG_DEBUG_TCG, Richard Henderson, 2021/03/12