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Re: Question about edge-triggered interrupt
From: |
Peter Maydell |
Subject: |
Re: Question about edge-triggered interrupt |
Date: |
Thu, 11 Mar 2021 13:17:34 +0000 |
On Thu, 11 Mar 2021 at 12:59, LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
> From the specification, I find that software will not clean the pending bit
> on interrupt controller via a register write.
>
> "When a vectored interrupt is selected and serviced, the hardware will
> automatically clear the
>
> corresponding pending bit in edge-triggered mode. In this case, software does
> not need to clear
>
> pending bit at all in the service routine."
>
> Hardware can always select a pending interrupt as it is cycle-driven. But
> QEMU is event-driven.
> I don't know if there is a chance to select other pending interrupts after
> serving the selected interrupt.
Something must change that the hardware (and thus the model) can use to
determine that it needs to do something else. The interrupt controller
must be able to tell when the interrupt is "selected and serviced"
somehow.
thanks
-- PMM
- Question about edge-triggered interrupt, LIU Zhiwei, 2021/03/10
- Re: Question about edge-triggered interrupt, Peter Maydell, 2021/03/11
- Re: Question about edge-triggered interrupt, LIU Zhiwei, 2021/03/11
- Re: Question about edge-triggered interrupt,
Peter Maydell <=
- Re: Question about edge-triggered interrupt, LIU Zhiwei, 2021/03/11
- Re: Question about edge-triggered interrupt, Peter Maydell, 2021/03/11
- Re: Question about edge-triggered interrupt, LIU Zhiwei, 2021/03/11
- Re: Question about edge-triggered interrupt, Peter Maydell, 2021/03/11
- Re: Question about edge-triggered interrupt, LIU Zhiwei, 2021/03/12
- Re: Question about edge-triggered interrupt, Peter Maydell, 2021/03/12
- Re: Question about edge-triggered interrupt, Alistair Francis, 2021/03/11
- Re: Question about edge-triggered interrupt, LIU Zhiwei, 2021/03/12