Re: [PATCH v2 09/22] tcg/riscv: Split out target constraints to tcg-target-con-str.h

[Richard Henderson]

On 1/15/21 12:13 PM, Alistair Francis wrote:
> On Fri, Jan 15, 2021 at 1:09 PM Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>  tcg/riscv/tcg-target-con-str.h | 21 ++++++++++++++
>>  tcg/riscv/tcg-target.h         |  1 +
>>  tcg/riscv/tcg-target.c.inc     | 50 ++++++++--------------------------
>>  3 files changed, 33 insertions(+), 39 deletions(-)
>>  create mode 100644 tcg/riscv/tcg-target-con-str.h
>>
>> diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h
>> new file mode 100644
>> index 0000000000..587fcd3593
>> --- /dev/null
>> +++ b/tcg/riscv/tcg-target-con-str.h
>> @@ -0,0 +1,21 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Define RISC-V target-specific operand constraints.
>> + * Copyright (c) 2021 Linaro
>> + */
>> +
>> +/*
>> + * Define constraint letters for register sets:
>> + * REGS(letter, register_mask)
>> + */
>> +REGS('r', ALL_GENERAL_REGS)
>> +REGS('L', ALL_QLDST_REGS)
>> +
>> +/*
>> + * Define constraint letters for constants:
>> + * CONST(letter, TCG_CT_CONST_* bit set)
>> + */
>> +CONST('I', TCG_CT_CONST_S12)
>> +CONST('N', TCG_CT_CONST_N12)
>> +CONST('M', TCG_CT_CONST_M12)
>> +CONST('Z', TCG_CT_CONST_ZERO)
>> diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
>> index 727c8df418..daf3ef7b5c 100644
>> --- a/tcg/riscv/tcg-target.h
>> +++ b/tcg/riscv/tcg-target.h
>> @@ -171,5 +171,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
>> uintptr_t, uintptr_t);
>>  #define TCG_TARGET_NEED_POOL_LABELS
>>
>>  #define TCG_TARGET_HAS_MEMORY_BSWAP 0
>> +#define TCG_TARGET_CON_STR_H
>>
>>  #endif
>> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
>> index 71c0badc02..185b569f4b 100644
>> --- a/tcg/riscv/tcg-target.c.inc
>> +++ b/tcg/riscv/tcg-target.c.inc
>> @@ -122,6 +122,17 @@ static const int tcg_target_call_oarg_regs[] = {
>>  #define TCG_CT_CONST_N12   0x400
>>  #define TCG_CT_CONST_M12   0x800
>>
>> +#define ALL_GENERAL_REGS  0xffffffffu
>> +#ifdef CONFIG_SOFTMMU
>> +#define ALL_QLDST_REGS \
>> +    (ALL_GENERAL_REGS & ~((1 << TCG_REG_A0) | (1 << TCG_REG_A1) | \
>> +                          (1 << TCG_REG_A2) | (1 << TCG_REG_A3) | \
>> +                          (1 << TCG_REG_A5)))
> 
> Why is this not TCG_REG_A4?

Typo, thanks.


r~