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[PATCH 5/6] target/mips: Convert Loongson [D]MOD[U].G opcodes to decodet
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 5/6] target/mips: Convert Loongson [D]MOD[U].G opcodes to decodetree |
Date: |
Tue, 12 Jan 2021 22:55:03 +0100 |
Convert the following opcodes to decodetree:
- MOD.G - mod 32-bit signed integers
- MODU.G - mod 32-bit unsigned integers
- DMOD.G - mod 64-bit signed integers
- DMODU.G - mod 64-bit unsigned integers
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/godson2.decode | 5 ++
target/mips/loong-ext.decode | 5 ++
target/mips/loong_translate.c | 116 ++++++++++++++++++++++++++++++++++
target/mips/translate.c | 86 -------------------------
4 files changed, 126 insertions(+), 86 deletions(-)
diff --git a/target/mips/godson2.decode b/target/mips/godson2.decode
index 0d5a72064d2..805452fa975 100644
--- a/target/mips/godson2.decode
+++ b/target/mips/godson2.decode
@@ -17,3 +17,8 @@ DIV.G 011111 ..... ..... ..... 00000 011010
@rs_rt_rd
DIVU.G 011111 ..... ..... ..... 00000 011011 @rs_rt_rd
DDIV.G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd
DDIVU.G 011111 ..... ..... ..... 00000 011111 @rs_rt_rd
+
+MOD.G 011111 ..... ..... ..... 00000 100010 @rs_rt_rd
+MODU.G 011111 ..... ..... ..... 00000 100011 @rs_rt_rd
+DMOD.G 011111 ..... ..... ..... 00000 100110 @rs_rt_rd
+DMODU.G 011111 ..... ..... ..... 00000 100111 @rs_rt_rd
diff --git a/target/mips/loong-ext.decode b/target/mips/loong-ext.decode
index 2e98262b81d..b0715894ee1 100644
--- a/target/mips/loong-ext.decode
+++ b/target/mips/loong-ext.decode
@@ -18,3 +18,8 @@ DIV.G 011100 ..... ..... ..... 00000 010100
@rs_rt_rd
DDIV.G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd
DIVU.G 011100 ..... ..... ..... 00000 010110 @rs_rt_rd
DDIVU.G 011100 ..... ..... ..... 00000 010111 @rs_rt_rd
+
+MOD.G 011100 ..... ..... ..... 00000 011100 @rs_rt_rd
+DMOD.G 011100 ..... ..... ..... 00000 011101 @rs_rt_rd
+MODU.G 011100 ..... ..... ..... 00000 011110 @rs_rt_rd
+DMODU.G 011100 ..... ..... ..... 00000 011111 @rs_rt_rd
diff --git a/target/mips/loong_translate.c b/target/mips/loong_translate.c
index 7b3304ec749..50609ce4178 100644
--- a/target/mips/loong_translate.c
+++ b/target/mips/loong_translate.c
@@ -147,6 +147,122 @@ static bool trans_DDIVU_G(DisasContext *s, arg_muldiv *a)
return gen_lext_DIVU_G(s, a->rt, a->rs, a->rd, true);
}
+static bool gen_lext_MOD_G(DisasContext *s, int rd, int rs, int rt,
+ bool is_double)
+{
+ TCGv t0, t1;
+ TCGLabel *l1, *l2, *l3;
+
+ if (is_double) {
+ if (TARGET_LONG_BITS != 64) {
+ return false;
+ }
+ check_mips_64(s);
+ }
+
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return true;
+ }
+
+ t0 = tcg_temp_local_new();
+ t1 = tcg_temp_local_new();
+ l1 = gen_new_label();
+ l2 = gen_new_label();
+ l3 = gen_new_label();
+
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+
+ if (!is_double) {
+ tcg_gen_ext32u_tl(t0, t0);
+ tcg_gen_ext32u_tl(t1, t1);
+ }
+ tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? -1LL << 63 : INT_MIN, l2);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
+ gen_set_label(l1);
+ tcg_gen_movi_tl(cpu_gpr[rd], 0);
+ tcg_gen_br(l3);
+ gen_set_label(l2);
+ tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
+ if (!is_double) {
+ tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
+ }
+ gen_set_label(l3);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ return true;
+}
+
+static bool trans_MOD_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_MOD_G(s, a->rt, a->rs, a->rd, false);
+}
+
+static bool trans_DMOD_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_MOD_G(s, a->rt, a->rs, a->rd, true);
+}
+
+static bool gen_lext_MODU_G(DisasContext *s, int rd, int rs, int rt,
+ bool is_double)
+{
+ TCGv t0, t1;
+ TCGLabel *l1, *l2;
+
+ if (is_double) {
+ if (TARGET_LONG_BITS != 64) {
+ return false;
+ }
+ check_mips_64(s);
+ }
+
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return true;
+ }
+
+ t0 = tcg_temp_local_new();
+ t1 = tcg_temp_local_new();
+ l1 = gen_new_label();
+ l2 = gen_new_label();
+
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+
+ if (!is_double) {
+ tcg_gen_ext32u_tl(t0, t0);
+ tcg_gen_ext32u_tl(t1, t1);
+ }
+ tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
+ tcg_gen_movi_tl(cpu_gpr[rd], 0);
+ tcg_gen_br(l2);
+ gen_set_label(l1);
+ tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
+ if (!is_double) {
+ tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
+ }
+ gen_set_label(l2);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ return true;
+}
+
+static bool trans_MODU_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_MODU_G(s, a->rt, a->rs, a->rd, false);
+}
+
+static bool trans_DMODU_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_MODU_G(s, a->rt, a->rs, a->rd, true);
+}
+
bool decode_loongson(DisasContext *ctx, uint32_t insn)
{
if ((ctx->insn_flags & INSN_LOONGSON2E)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 69463e3b42d..144e51b063a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -342,10 +342,6 @@ enum {
OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2,
OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2,
OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,
- OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2,
- OPC_DMOD_G_2F = 0x1d | OPC_SPECIAL2,
- OPC_MODU_G_2F = 0x1e | OPC_SPECIAL2,
- OPC_DMODU_G_2F = 0x1f | OPC_SPECIAL2,
/* Misc */
OPC_CLZ = 0x20 | OPC_SPECIAL2,
OPC_CLO = 0x21 | OPC_SPECIAL2,
@@ -379,10 +375,6 @@ enum {
OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3,
OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3,
OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,
- OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3,
- OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3,
- OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3,
- OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3,
/* MIPS DSP Load */
OPC_LX_DSP = 0x0A | OPC_SPECIAL3,
@@ -4995,10 +4987,6 @@ static void gen_loongson_integer(DisasContext *ctx,
uint32_t opc,
t0 = tcg_temp_new();
t1 = tcg_temp_new();
break;
- default:
- t0 = tcg_temp_local_new();
- t1 = tcg_temp_local_new();
- break;
}
gen_load_gpr(t0, rs);
@@ -5017,42 +5005,6 @@ static void gen_loongson_integer(DisasContext *ctx,
uint32_t opc,
tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
break;
- case OPC_MOD_G_2E:
- case OPC_MOD_G_2F:
- {
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- TCGLabel *l3 = gen_new_label();
- tcg_gen_ext32u_tl(t0, t0);
- tcg_gen_ext32u_tl(t1, t1);
- tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2);
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2);
- gen_set_label(l1);
- tcg_gen_movi_tl(cpu_gpr[rd], 0);
- tcg_gen_br(l3);
- gen_set_label(l2);
- tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- gen_set_label(l3);
- }
- break;
- case OPC_MODU_G_2E:
- case OPC_MODU_G_2F:
- {
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- tcg_gen_ext32u_tl(t0, t0);
- tcg_gen_ext32u_tl(t1, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
- tcg_gen_movi_tl(cpu_gpr[rd], 0);
- tcg_gen_br(l2);
- gen_set_label(l1);
- tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- gen_set_label(l2);
- }
- break;
#if defined(TARGET_MIPS64)
case OPC_DMULT_G_2E:
case OPC_DMULT_G_2F:
@@ -5062,36 +5014,6 @@ static void gen_loongson_integer(DisasContext *ctx,
uint32_t opc,
case OPC_DMULTU_G_2F:
tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
break;
- case OPC_DMOD_G_2E:
- case OPC_DMOD_G_2F:
- {
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- TCGLabel *l3 = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
- gen_set_label(l1);
- tcg_gen_movi_tl(cpu_gpr[rd], 0);
- tcg_gen_br(l3);
- gen_set_label(l2);
- tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
- gen_set_label(l3);
- }
- break;
- case OPC_DMODU_G_2E:
- case OPC_DMODU_G_2F:
- {
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
- tcg_gen_movi_tl(cpu_gpr[rd], 0);
- tcg_gen_br(l2);
- gen_set_label(l1);
- tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
- gen_set_label(l2);
- }
- break;
#endif
}
@@ -27069,8 +26991,6 @@ static void decode_opc_special2_legacy(CPUMIPSState
*env, DisasContext *ctx)
break;
case OPC_MULT_G_2F:
case OPC_MULTU_G_2F:
- case OPC_MOD_G_2F:
- case OPC_MODU_G_2F:
check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
gen_loongson_integer(ctx, op1, rd, rs, rt);
break;
@@ -27100,8 +27020,6 @@ static void decode_opc_special2_legacy(CPUMIPSState
*env, DisasContext *ctx)
break;
case OPC_DMULT_G_2F:
case OPC_DMULTU_G_2F:
- case OPC_DMOD_G_2F:
- case OPC_DMODU_G_2F:
check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
gen_loongson_integer(ctx, op1, rd, rs, rt);
break;
@@ -27237,8 +27155,6 @@ static void decode_opc_special3_legacy(CPUMIPSState
*env, DisasContext *ctx)
op1 = MASK_SPECIAL3(ctx->opcode);
switch (op1) {
- case OPC_MOD_G_2E:
- case OPC_MODU_G_2E:
case OPC_MULT_G_2E:
case OPC_MULTU_G_2E:
/*
@@ -27508,8 +27424,6 @@ static void decode_opc_special3_legacy(CPUMIPSState
*env, DisasContext *ctx)
#if defined(TARGET_MIPS64)
case OPC_DMULT_G_2E:
case OPC_DMULTU_G_2E:
- case OPC_DMOD_G_2E:
- case OPC_DMODU_G_2E:
check_insn(ctx, INSN_LOONGSON2E);
gen_loongson_integer(ctx, op1, rd, rs, rt);
break;
--
2.26.2
- [PATCH 1/6] target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP, (continued)
- [PATCH 1/6] target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP, Philippe Mathieu-Daudé, 2021/01/12
- [PATCH 2/6] target/mips: Convert Loongson DDIV.G opcodes to decodetree, Philippe Mathieu-Daudé, 2021/01/12
- [PATCH 4/6] target/mips: Convert Loongson [D]DIVU.G opcodes to decodetree, Philippe Mathieu-Daudé, 2021/01/12
- [PATCH 3/6] target/mips: Convert Loongson DIV.G opcodes to decodetree, Philippe Mathieu-Daudé, 2021/01/12
- [PATCH 5/6] target/mips: Convert Loongson [D]MOD[U].G opcodes to decodetree,
Philippe Mathieu-Daudé <=
- [PATCH 6/6] target/mips: Convert Loongson [D]MULT[U].G opcodes to decodetree, Philippe Mathieu-Daudé, 2021/01/12
- Re: [PATCH 0/6] target/mips: Convert Loongson LEXT opcodes to decodetree, Jiaxun Yang, 2021/01/12
- Re: [PATCH 0/6] target/mips: Convert Loongson LEXT opcodes to decodetree, Richard Henderson, 2021/01/21