Re: [PATCH 4/6] target/mips: Convert Loongson [D]DIVU.G opcodes to decodetree

[Richard Henderson]

On 1/12/21 11:55 AM, Philippe Mathieu-Daudé wrote:
> Convert DIVU.G (divide 32-bit unsigned integers) and DDIVU.G
> (divide 64-bit unsigned integers) opcodes to decodetree.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/godson2.decode    |  2 ++
>  target/mips/loong-ext.decode  |  2 ++
>  target/mips/loong_translate.c | 55 +++++++++++++++++++++++++++++++++++
>  target/mips/translate.c       | 37 -----------------------
>  4 files changed, 59 insertions(+), 37 deletions(-)
> 
> diff --git a/target/mips/godson2.decode b/target/mips/godson2.decode
> index b56a93a1999..0d5a72064d2 100644
> --- a/target/mips/godson2.decode
> +++ b/target/mips/godson2.decode
> @@ -14,4 +14,6 @@
>  @rs_rt_rd       ...... rs:5  rt:5  rd:5  ..... ......   &muldiv
>  
>  DIV.G           011111 ..... ..... ..... 00000 011010   @rs_rt_rd
> +DIVU.G          011111 ..... ..... ..... 00000 011011   @rs_rt_rd
>  DDIV.G          011111 ..... ..... ..... 00000 011110   @rs_rt_rd
> +DDIVU.G         011111 ..... ..... ..... 00000 011111   @rs_rt_rd
> diff --git a/target/mips/loong-ext.decode b/target/mips/loong-ext.decode
> index 331c2226ae3..2e98262b81d 100644
> --- a/target/mips/loong-ext.decode
> +++ b/target/mips/loong-ext.decode
> @@ -16,3 +16,5 @@
>  
>  DIV.G           011100 ..... ..... ..... 00000 010100   @rs_rt_rd
>  DDIV.G          011100 ..... ..... ..... 00000 010101   @rs_rt_rd
> +DIVU.G          011100 ..... ..... ..... 00000 010110   @rs_rt_rd
> +DDIVU.G         011100 ..... ..... ..... 00000 010111   @rs_rt_rd
> diff --git a/target/mips/loong_translate.c b/target/mips/loong_translate.c
> index 634d4ba8031..7b3304ec749 100644
> --- a/target/mips/loong_translate.c
> +++ b/target/mips/loong_translate.c
> @@ -92,6 +92,61 @@ static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a)
>      return gen_lext_DIV_G(s, a->rt, a->rs, a->rd, true);
>  }
>  
> +static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt,
> +                            bool is_double)
> +{
> +    TCGv t0, t1;
> +    TCGLabel *l1, *l2;
> +
> +    if (is_double) {
> +        if (TARGET_LONG_BITS != 64) {
> +            return false;
> +        }
> +        check_mips_64(s);
> +    }
> +
> +    if (rd == 0) {
> +        /* Treat as NOP. */
> +        return true;
> +    }
> +
> +    t0 = tcg_temp_local_new();
> +    t1 = tcg_temp_local_new();
> +    l1 = gen_new_label();
> +    l2 = gen_new_label();
> +
> +    gen_load_gpr(t0, rs);
> +    gen_load_gpr(t1, rt);
> +
> +    if (!is_double) {
> +        tcg_gen_ext32u_tl(t0, t0);
> +        tcg_gen_ext32u_tl(t1, t1);
> +    }
> +    tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
> +    tcg_gen_movi_tl(cpu_gpr[rd], 0);
> +
> +    tcg_gen_br(l2);
> +    gen_set_label(l1);
> +    tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
> +    tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);

this extend should be conditional on !is_double.

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~