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[PATCH v4 12/16] target/riscv: cpu: Remove compile time XLEN checks
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From: |
Alistair Francis |
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Subject: |
[PATCH v4 12/16] target/riscv: cpu: Remove compile time XLEN checks |
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Date: |
Wed, 16 Dec 2020 10:22:56 -0800 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
target/riscv/cpu.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7d6f032122..47b738c314 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -240,10 +240,10 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,
int flags)
#ifndef CONFIG_USER_ONLY
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ",
(target_ulong)env->mstatus);
-#ifdef TARGET_RISCV32
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
- (target_ulong)(env->mstatus >> 32));
-#endif
+ if (riscv_cpu_is_32bit(env)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
+ (target_ulong)(env->mstatus >> 32));
+ }
if (riscv_has_ext(env, RVH)) {
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ",
@@ -356,11 +356,12 @@ static void riscv_cpu_reset(DeviceState *dev)
static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
-#if defined(TARGET_RISCV32)
- info->print_insn = print_insn_riscv32;
-#elif defined(TARGET_RISCV64)
- info->print_insn = print_insn_riscv64;
-#endif
+ RISCVCPU *cpu = RISCV_CPU(s);
+ if (riscv_cpu_is_32bit(&cpu->env)) {
+ info->print_insn = print_insn_riscv32;
+ } else {
+ info->print_insn = print_insn_riscv64;
+ }
}
static void riscv_cpu_realize(DeviceState *dev, Error **errp)
--
2.29.2
- [PATCH v4 01/16] hw/riscv: Expand the is 32-bit check to support more CPUs, (continued)
- [PATCH v4 01/16] hw/riscv: Expand the is 32-bit check to support more CPUs, Alistair Francis, 2020/12/16
- [PATCH v4 04/16] riscv: virt: Remove target macro conditionals, Alistair Francis, 2020/12/16
- [PATCH v4 05/16] hw/riscv: boot: Remove compile time XLEN checks, Alistair Francis, 2020/12/16
- [PATCH v4 06/16] hw/riscv: virt: Remove compile time XLEN checks, Alistair Francis, 2020/12/16
- [PATCH v4 07/16] hw/riscv: spike: Remove compile time XLEN checks, Alistair Francis, 2020/12/16
- [PATCH v4 08/16] hw/riscv: sifive_u: Remove compile time XLEN checks, Alistair Francis, 2020/12/16
- [PATCH v4 09/16] target/riscv: fpu_helper: Match function defs in HELPER macros, Alistair Francis, 2020/12/16
- [PATCH v4 10/16] target/riscv: Add a riscv_cpu_is_32bit() helper function, Alistair Francis, 2020/12/16
- [PATCH v4 11/16] target/riscv: Specify the XLEN for CPUs, Alistair Francis, 2020/12/16
- [PATCH v4 12/16] target/riscv: cpu: Remove compile time XLEN checks,
Alistair Francis <=
- [PATCH v4 13/16] target/riscv: cpu_helper: Remove compile time XLEN checks, Alistair Francis, 2020/12/16
- [PATCH v4 14/16] target/riscv: csr: Remove compile time XLEN checks, Alistair Francis, 2020/12/16
- [PATCH v4 15/16] target/riscv: cpu: Set XLEN independently from target, Alistair Francis, 2020/12/16
- [PATCH v4 16/16] hw/riscv: Use the CPU to determine if 32-bit, Alistair Francis, 2020/12/16