[PATCH v4 09/16] target/riscv: fpu_helper: Match function defs in HELPER

qemu-devel

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[PATCH v4 09/16] target/riscv: fpu_helper: Match function defs in HELPER

From:	Alistair Francis
Subject:	[PATCH v4 09/16] target/riscv: fpu_helper: Match function defs in HELPER macros
Date:	Wed, 16 Dec 2020 10:22:48 -0800

Update the function definitions generated in helper.h to match the
actual function implementations.

Also remove all compile time XLEN checks when building.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h     | 24 ++++++++----------------
 target/riscv/fpu_helper.c |  8 --------
 2 files changed, 8 insertions(+), 24 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 939731c345..e3f3f41e89 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -27,16 +27,12 @@ DEF_HELPER_FLAGS_3(flt_s, TCG_CALL_NO_RWG, tl, env, i64, 
i64)
 DEF_HELPER_FLAGS_3(feq_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
 DEF_HELPER_FLAGS_2(fcvt_w_s, TCG_CALL_NO_RWG, tl, env, i64)
 DEF_HELPER_FLAGS_2(fcvt_wu_s, TCG_CALL_NO_RWG, tl, env, i64)
-#if defined(TARGET_RISCV64)
-DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, tl, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, tl, env, i64)
-#endif
+DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, i64, env, i64)
 DEF_HELPER_FLAGS_2(fcvt_s_w, TCG_CALL_NO_RWG, i64, env, tl)
 DEF_HELPER_FLAGS_2(fcvt_s_wu, TCG_CALL_NO_RWG, i64, env, tl)
-#if defined(TARGET_RISCV64)
-DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, tl)
-DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, tl)
-#endif
+DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, i64)
 DEF_HELPER_FLAGS_1(fclass_s, TCG_CALL_NO_RWG_SE, tl, i64)
 
 /* Floating Point - Double Precision */
@@ -54,16 +50,12 @@ DEF_HELPER_FLAGS_3(flt_d, TCG_CALL_NO_RWG, tl, env, i64, 
i64)
 DEF_HELPER_FLAGS_3(feq_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
 DEF_HELPER_FLAGS_2(fcvt_w_d, TCG_CALL_NO_RWG, tl, env, i64)
 DEF_HELPER_FLAGS_2(fcvt_wu_d, TCG_CALL_NO_RWG, tl, env, i64)
-#if defined(TARGET_RISCV64)
-DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, tl, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, tl, env, i64)
-#endif
+DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, i64, env, i64)
 DEF_HELPER_FLAGS_2(fcvt_d_w, TCG_CALL_NO_RWG, i64, env, tl)
 DEF_HELPER_FLAGS_2(fcvt_d_wu, TCG_CALL_NO_RWG, i64, env, tl)
-#if defined(TARGET_RISCV64)
-DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl)
-DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
-#endif
+DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, i64)
 DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
 
 /* Special functions */
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index bb346a8249..7c4ab92ecb 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -223,7 +223,6 @@ target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t 
rs1)
     return (int32_t)float32_to_uint32(frs1, &env->fp_status);
 }
 
-#if defined(TARGET_RISCV64)
 uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
 {
     float32 frs1 = check_nanbox_s(rs1);
@@ -235,7 +234,6 @@ uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
     float32 frs1 = check_nanbox_s(rs1);
     return float32_to_uint64(frs1, &env->fp_status);
 }
-#endif
 
 uint64_t helper_fcvt_s_w(CPURISCVState *env, target_ulong rs1)
 {
@@ -247,7 +245,6 @@ uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong 
rs1)
     return nanbox_s(uint32_to_float32((uint32_t)rs1, &env->fp_status));
 }
 
-#if defined(TARGET_RISCV64)
 uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1)
 {
     return nanbox_s(int64_to_float32(rs1, &env->fp_status));
@@ -257,7 +254,6 @@ uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1)
 {
     return nanbox_s(uint64_to_float32(rs1, &env->fp_status));
 }
-#endif
 
 target_ulong helper_fclass_s(uint64_t rs1)
 {
@@ -336,7 +332,6 @@ target_ulong helper_fcvt_wu_d(CPURISCVState *env, uint64_t 
frs1)
     return (int32_t)float64_to_uint32(frs1, &env->fp_status);
 }
 
-#if defined(TARGET_RISCV64)
 uint64_t helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
 {
     return float64_to_int64(frs1, &env->fp_status);
@@ -346,7 +341,6 @@ uint64_t helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
 {
     return float64_to_uint64(frs1, &env->fp_status);
 }
-#endif
 
 uint64_t helper_fcvt_d_w(CPURISCVState *env, target_ulong rs1)
 {
@@ -358,7 +352,6 @@ uint64_t helper_fcvt_d_wu(CPURISCVState *env, target_ulong 
rs1)
     return uint32_to_float64((uint32_t)rs1, &env->fp_status);
 }
 
-#if defined(TARGET_RISCV64)
 uint64_t helper_fcvt_d_l(CPURISCVState *env, uint64_t rs1)
 {
     return int64_to_float64(rs1, &env->fp_status);
@@ -368,7 +361,6 @@ uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1)
 {
     return uint64_to_float64(rs1, &env->fp_status);
 }
-#endif
 
 target_ulong helper_fclass_d(uint64_t frs1)
 {
-- 
2.29.2

[Prev in Thread]

Current Thread

[Next in Thread]

[PATCH v4 00/16] RISC-V: Start to remove xlen preprocess, Alistair Francis, 2020/12/16
- [PATCH v4 02/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU, Alistair Francis, 2020/12/16
- [PATCH v4 03/16] riscv: spike: Remove target macro conditionals, Alistair Francis, 2020/12/16
- [PATCH v4 01/16] hw/riscv: Expand the is 32-bit check to support more CPUs, Alistair Francis, 2020/12/16
- [PATCH v4 04/16] riscv: virt: Remove target macro conditionals, Alistair Francis, 2020/12/16
- [PATCH v4 05/16] hw/riscv: boot: Remove compile time XLEN checks, Alistair Francis, 2020/12/16
- [PATCH v4 06/16] hw/riscv: virt: Remove compile time XLEN checks, Alistair Francis, 2020/12/16
- [PATCH v4 07/16] hw/riscv: spike: Remove compile time XLEN checks, Alistair Francis, 2020/12/16
- [PATCH v4 08/16] hw/riscv: sifive_u: Remove compile time XLEN checks, Alistair Francis, 2020/12/16
  - Re: [PATCH v4 08/16] hw/riscv: sifive_u: Remove compile time XLEN checks, Bin Meng, 2020/12/17
- [PATCH v4 09/16] target/riscv: fpu_helper: Match function defs in HELPER macros, Alistair Francis <=
- [PATCH v4 10/16] target/riscv: Add a riscv_cpu_is_32bit() helper function, Alistair Francis, 2020/12/16
- [PATCH v4 11/16] target/riscv: Specify the XLEN for CPUs, Alistair Francis, 2020/12/16
- [PATCH v4 12/16] target/riscv: cpu: Remove compile time XLEN checks, Alistair Francis, 2020/12/16
  - Re: [PATCH v4 12/16] target/riscv: cpu: Remove compile time XLEN checks, Bin Meng, 2020/12/17
- [PATCH v4 13/16] target/riscv: cpu_helper: Remove compile time XLEN checks, Alistair Francis, 2020/12/16
  - Re: [PATCH v4 13/16] target/riscv: cpu_helper: Remove compile time XLEN checks, Bin Meng, 2020/12/17
- [PATCH v4 14/16] target/riscv: csr: Remove compile time XLEN checks, Alistair Francis, 2020/12/16
  - Re: [PATCH v4 14/16] target/riscv: csr: Remove compile time XLEN checks, Bin Meng, 2020/12/17
- [PATCH v4 15/16] target/riscv: cpu: Set XLEN independently from target, Alistair Francis, 2020/12/16
- [PATCH v4 16/16] hw/riscv: Use the CPU to determine if 32-bit, Alistair Francis, 2020/12/16

Prev by Date: [PATCH v4 08/16] hw/riscv: sifive_u: Remove compile time XLEN checks
Next by Date: [PATCH v4 10/16] target/riscv: Add a riscv_cpu_is_32bit() helper function
Previous by thread: Re: [PATCH v4 08/16] hw/riscv: sifive_u: Remove compile time XLEN checks
Next by thread: [PATCH v4 10/16] target/riscv: Add a riscv_cpu_is_32bit() helper function
Index(es):
- Date
- Thread