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[RFC v2 14/15] target/riscv: rvb: add/sub with postfix zero-extend
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From: |
frank . chang |
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Subject: |
[RFC v2 14/15] target/riscv: rvb: add/sub with postfix zero-extend |
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Date: |
Wed, 16 Dec 2020 10:01:39 +0800 |
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32-64.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 22 ++++++++++++++++++++++
target/riscv/translate.c | 6 ++++++
3 files changed, 31 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 1059cab5aa4..f819028266c 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -107,6 +107,7 @@ gorcw 0010100 .......... 101 ..... 0111011 @r
sh1addu_w 0010000 .......... 010 ..... 0111011 @r
sh2addu_w 0010000 .......... 100 ..... 0111011 @r
sh3addu_w 0010000 .......... 110 ..... 0111011 @r
+addu_w 0000100 .......... 000 ..... 0111011 @r
sbsetiw 0010100 .......... 001 ..... 0011011 @sh5
sbclriw 0100100 .......... 001 ..... 0011011 @sh5
@@ -116,3 +117,5 @@ sroiw 0010000 .......... 101 ..... 0011011 @sh5
roriw 0110000 .......... 101 ..... 0011011 @sh5
greviw 0110100 .......... 101 ..... 0011011 @sh5
gorciw 0010100 .......... 101 ..... 0011011 @sh5
+
+slliu_w 00001. ........... 001 ..... 0011011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index 07fe662b005..323ca5eccee 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -441,4 +441,26 @@ GEN_TRANS_SHADDU_W(1)
GEN_TRANS_SHADDU_W(2)
GEN_TRANS_SHADDU_W(3)
+static bool trans_addu_w(DisasContext *ctx, arg_addu_w *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_addu_w);
+}
+
+static bool trans_slliu_w(DisasContext *ctx, arg_slliu_w *a)
+{
+ TCGv source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ if (a->shamt < 32) {
+ tcg_gen_deposit_z_i64(source1, source1, a->shamt, 32);
+ } else {
+ tcg_gen_shli_i64(source1, source1, a->shamt);
+ }
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ return true;
+}
+
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f9385bbcd4f..84e55880234 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -955,6 +955,12 @@ GEN_SHADDU_W(1)
GEN_SHADDU_W(2)
GEN_SHADDU_W(3)
+static void gen_addu_w(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_ext32u_tl(arg1, arg1);
+ tcg_gen_add_tl(ret, arg1, arg2);
+}
+
#endif
static bool gen_arith(DisasContext *ctx, arg_r *a,
--
2.17.1
- [RFC v2 08/15] target/riscv: rvb: single-bit instructions, (continued)
- [RFC v2 08/15] target/riscv: rvb: single-bit instructions, frank . chang, 2020/12/15
- [RFC v2 09/15] target/riscv: rvb: shift ones, frank . chang, 2020/12/15
- [RFC v2 10/15] target/riscv: rvb: rotate (left/right), frank . chang, 2020/12/15
- [RFC v2 12/15] target/riscv: rvb: generalized or-combine, frank . chang, 2020/12/15
- [RFC v2 13/15] target/riscv: rvb: address calculation, frank . chang, 2020/12/15
- [RFC v2 14/15] target/riscv: rvb: add/sub with postfix zero-extend,
frank . chang <=
- [RFC v2 11/15] target/riscv: rvb: generalized reverse, frank . chang, 2020/12/15
- [RFC v2 15/15] target/riscv: rvb: support and turn on B-extension from command line, frank . chang, 2020/12/15