[PATCH v2 11/15] target/riscv: Specify the XLEN for CPUs

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[PATCH v2 11/15] target/riscv: Specify the XLEN for CPUs

From:	Alistair Francis
Subject:	[PATCH v2 11/15] target/riscv: Specify the XLEN for CPUs
Date:	Tue, 8 Dec 2020 14:56:39 -0800

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
---
 target/riscv/cpu.c | 33 +++++++++++++++++++++++----------
 1 file changed, 23 insertions(+), 10 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 32a6916b8a..7d6f032122 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -158,22 +158,36 @@ static void riscv_base_cpu_init(Object *obj)
     set_misa(env, 0);
 }
 
-static void rvxx_sifive_u_cpu_init(Object *obj)
+#ifdef TARGET_RISCV64
+static void rv64_sifive_u_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-    set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+    set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
 }
 
-static void rvxx_sifive_e_cpu_init(Object *obj)
+static void rv64_sifive_e_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-    set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
+    set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 }
+#else
+static void rv32_sifive_u_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+    set_priv_version(env, PRIV_VERSION_1_10_0);
+}
 
-#if defined(TARGET_RISCV32)
+static void rv32_sifive_e_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+    set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
+    set_priv_version(env, PRIV_VERSION_1_10_0);
+    qdev_prop_set_bit(DEVICE(obj), "mmu", false);
+}
 
 static void rv32_ibex_cpu_init(Object *obj)
 {
@@ -191,7 +205,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
     set_resetvec(env, DEFAULT_RSTVEC);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 }
-
 #endif
 
 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
@@ -643,13 +656,13 @@ static const TypeInfo riscv_cpu_type_infos[] = {
 #if defined(TARGET_RISCV32)
     DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           riscv_base_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
-    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rvxx_sifive_e_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32_sifive_e_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32_imafcu_nommu_cpu_init),
-    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rvxx_sifive_u_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32_sifive_u_cpu_init),
 #elif defined(TARGET_RISCV64)
     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           riscv_base_cpu_init),
-    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rvxx_sifive_e_cpu_init),
-    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rvxx_sifive_u_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64_sifive_e_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64_sifive_u_cpu_init),
 #endif
 };
 
-- 
2.29.2

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Re: [PATCH v2 05/15] hw/riscv: boot: Remove compile time XLEN checks, (continued)
- [PATCH v2 06/15] hw/riscv: virt: Remove compile time XLEN checks, Alistair Francis, 2020/12/08
- [PATCH v2 07/15] hw/riscv: spike: Remove compile time XLEN checks, Alistair Francis, 2020/12/08
- [PATCH v2 09/15] target/riscv: fpu_helper: Match function defs in HELPER macros, Alistair Francis, 2020/12/08
  - Re: [PATCH v2 09/15] target/riscv: fpu_helper: Match function defs in HELPER macros, Richard Henderson, 2020/12/09
    - Re: [PATCH v2 09/15] target/riscv: fpu_helper: Match function defs in HELPER macros, Alistair Francis, 2020/12/09
- [PATCH v2 08/15] hw/riscv: sifive_u: Remove compile time XLEN checks, Alistair Francis, 2020/12/08
- [PATCH v2 10/15] target/riscv: Add a riscv_cpu_is_32bit() helper function, Alistair Francis, 2020/12/08
  - Re: [PATCH v2 10/15] target/riscv: Add a riscv_cpu_is_32bit() helper function, Richard Henderson, 2020/12/09
    - Re: [PATCH v2 10/15] target/riscv: Add a riscv_cpu_is_32bit() helper function, Alistair Francis, 2020/12/09
- [PATCH v2 11/15] target/riscv: Specify the XLEN for CPUs, Alistair Francis <=
  - Re: [PATCH v2 11/15] target/riscv: Specify the XLEN for CPUs, Richard Henderson, 2020/12/09
    - Re: [PATCH v2 11/15] target/riscv: Specify the XLEN for CPUs, Alistair Francis, 2020/12/09
- [PATCH v2 12/15] target/riscv: cpu: Remove compile time XLEN checks, Alistair Francis, 2020/12/08
  - Re: [PATCH v2 12/15] target/riscv: cpu: Remove compile time XLEN checks, Richard Henderson, 2020/12/09
- [PATCH v2 13/15] target/riscv: cpu_helper: Remove compile time XLEN checks, Alistair Francis, 2020/12/08
  - Re: [PATCH v2 13/15] target/riscv: cpu_helper: Remove compile time XLEN checks, Richard Henderson, 2020/12/09
- [PATCH v2 14/15] target/riscv: csr: Remove compile time XLEN checks, Alistair Francis, 2020/12/08
  - Re: [PATCH v2 14/15] target/riscv: csr: Remove compile time XLEN checks, Richard Henderson, 2020/12/09
    - Re: [PATCH v2 14/15] target/riscv: csr: Remove compile time XLEN checks, Alistair Francis, 2020/12/09
- [PATCH v2 15/15] target/riscv: cpu: Set XLEN independently from target, Alistair Francis, 2020/12/08

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