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[PATCH 2/5] target/mips: Introduce ase_mt_available() helper
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 2/5] target/mips: Introduce ase_mt_available() helper |
Date: |
Fri, 4 Dec 2020 23:26:19 +0100 |
Instead of accessing CP0_Config3 directly and checking
the 'Multi-Threading Present' bit, introduce an helper
to simplify code review.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/cpu.h | 7 +++++++
hw/mips/cps.c | 3 +--
target/mips/cp0_helper.c | 2 +-
target/mips/cpu.c | 2 +-
target/mips/helper.c | 2 +-
target/mips/translate.c | 2 +-
6 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 2639b0ea06c..82c60a34751 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1289,6 +1289,13 @@ int cpu_mips_signal_handler(int host_signum, void
*pinfo, void *puc);
bool cpu_supports_cps_smp(const char *cpu_type);
bool cpu_supports_isa(const char *cpu_type, uint64_t isa);
+
+/* Check presence of multi-threading ASE implementation */
+static inline bool ase_mt_available(CPUMIPSState *env)
+{
+ return env->CP0_Config3 & (1 << CP0C3_MT);
+}
+
void cpu_set_exception_base(int vp_index, target_ulong address);
/* mips_int.c */
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index 962b1b0b87c..7a0d289efaf 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -58,8 +58,7 @@ static void main_cpu_reset(void *opaque)
static bool cpu_mips_itu_supported(CPUMIPSState *env)
{
- bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) ||
- (env->CP0_Config3 & (1 << CP0C3_MT));
+ bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || ase_mt_available(env);
return is_mt && !kvm_enabled();
}
diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c
index caaaefcc8ad..9718c93d18c 100644
--- a/target/mips/cp0_helper.c
+++ b/target/mips/cp0_helper.c
@@ -1166,7 +1166,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong
arg1)
old = env->CP0_EntryHi;
val = (arg1 & mask) | (old & ~mask);
env->CP0_EntryHi = val;
- if (env->CP0_Config3 & (1 << CP0C3_MT)) {
+ if (ase_mt_available(env)) {
sync_c0_entryhi(env, env->current_tc);
}
/* If the ASID changes, flush qemu's TLB. */
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 76d50b00b42..c03e5acf5bc 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -74,7 +74,7 @@ static bool mips_cpu_has_work(CPUState *cs)
}
/* MIPS-MT has the ability to halt the CPU. */
- if (env->CP0_Config3 & (1 << CP0C3_MT)) {
+ if (ase_mt_available(env)) {
/*
* The QEMU model will issue an _WAKE request whenever the CPUs
* should be woken up.
diff --git a/target/mips/helper.c b/target/mips/helper.c
index cc46ea887e5..608fe1512a3 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -419,7 +419,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ulong
val)
tlb_flush(env_cpu(env));
}
#endif
- if (env->CP0_Config3 & (1 << CP0C3_MT)) {
+ if (ase_mt_available(env)) {
sync_c0_status(env, env, env->current_tc);
} else {
compute_hflags(env);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 0db032fc5fb..ee45dce9a50 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31921,7 +31921,7 @@ void cpu_state_reset(CPUMIPSState *env)
cpu_mips_store_count(env, 1);
- if (env->CP0_Config3 & (1 << CP0C3_MT)) {
+ if (ase_mt_available(env)) {
int i;
/* Only TC0 on VPE 0 starts as active. */
--
2.26.2
- [PATCH 0/5] mips: Sanitize Multi-Threading ASE, Philippe Mathieu-Daudé, 2020/12/04
- [PATCH 1/5] target/mips: Remove mips_def_t unused argument from mvp_init(), Philippe Mathieu-Daudé, 2020/12/04
- [PATCH 2/5] target/mips: Introduce ase_mt_available() helper,
Philippe Mathieu-Daudé <=
- [PATCH 3/5] target/mips: Do not initialize MT registers if MT ASE absent, Philippe Mathieu-Daudé, 2020/12/04
- [PATCH 5/5] hw/mips/malta: Rewrite CP0_MVPConf0 access using deposit(), Philippe Mathieu-Daudé, 2020/12/04
- [PATCH 4/5] hw/mips/malta: Do not initialize MT registers if MT ASE absent, Philippe Mathieu-Daudé, 2020/12/04
- Re: [PATCH 0/5] mips: Sanitize Multi-Threading ASE, Philippe Mathieu-Daudé, 2020/12/07