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[PULL v2 13/19] hw/riscv: microchip_pfsoc: Connect the IOSCB module
From: |
Alistair Francis |
Subject: |
[PULL v2 13/19] hw/riscv: microchip_pfsoc: Connect the IOSCB module |
Date: |
Tue, 3 Nov 2020 07:21:44 -0800 |
From: Bin Meng <bin.meng@windriver.com>
Previously IOSCB_CFG was created as an unimplemented device. With
the new IOSCB model, its memory range is already covered by the
IOSCB hence remove the previous unimplemented device creation in
the SoC codes.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-6-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/microchip_pfsoc.h | 4 +++-
hw/riscv/microchip_pfsoc.c | 13 ++++++++-----
hw/riscv/Kconfig | 1 +
3 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/include/hw/riscv/microchip_pfsoc.h
b/include/hw/riscv/microchip_pfsoc.h
index 5b81e26241..a244ae6d39 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -25,6 +25,7 @@
#include "hw/char/mchp_pfsoc_mmuart.h"
#include "hw/dma/sifive_pdma.h"
#include "hw/misc/mchp_pfsoc_dmc.h"
+#include "hw/misc/mchp_pfsoc_ioscb.h"
#include "hw/net/cadence_gem.h"
#include "hw/sd/cadence_sdhci.h"
@@ -40,6 +41,7 @@ typedef struct MicrochipPFSoCState {
DeviceState *plic;
MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy;
MchpPfSoCDdrCfgState ddr_cfg;
+ MchpPfSoCIoscbState ioscb;
MchpPfSoCMMUartState *serial0;
MchpPfSoCMMUartState *serial1;
MchpPfSoCMMUartState *serial2;
@@ -99,7 +101,7 @@ enum {
MICROCHIP_PFSOC_GPIO2,
MICROCHIP_PFSOC_ENVM_CFG,
MICROCHIP_PFSOC_ENVM_DATA,
- MICROCHIP_PFSOC_IOSCB_CFG,
+ MICROCHIP_PFSOC_IOSCB,
MICROCHIP_PFSOC_DRAM,
};
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 3c504f7c03..438e0c464d 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -16,6 +16,7 @@
* 5) SiFive Platform DMA (Direct Memory Access Controller)
* 6) GEM (Gigabit Ethernet MAC Controller)
* 7) DMC (DDR Memory Controller)
+ * 8) IOSCB modules
*
* This board currently generates devicetree dynamically that indicates at
least
* two harts and up to five harts.
@@ -118,7 +119,7 @@ static const struct MemmapEntry {
[MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
- [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
+ [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
[MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
};
@@ -162,6 +163,8 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
object_initialize_child(obj, "sd-controller", &s->sdhci,
TYPE_CADENCE_SDHCI);
+
+ object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB);
}
static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
@@ -373,10 +376,10 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev,
Error **errp)
memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
envm_data);
- /* IOSCBCFG */
- create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
- memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
- memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
+ /* IOSCB */
+ sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
+ memmap[MICROCHIP_PFSOC_IOSCB].base);
}
static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index c8e50bde99..8f043e38e0 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -5,6 +5,7 @@ config MICROCHIP_PFSOC
bool
select CADENCE_SDHCI
select MCHP_PFSOC_DMC
+ select MCHP_PFSOC_IOSCB
select MCHP_PFSOC_MMUART
select MSI_NONBROKEN
select SIFIVE_CLINT
--
2.28.0
- [PULL v2 03/19] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit, (continued)
- [PULL v2 03/19] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit, Alistair Francis, 2020/11/03
- [PULL v2 05/19] target/riscv: Add PMP state description, Alistair Francis, 2020/11/03
- [PULL v2 06/19] target/riscv: Add H extension state description, Alistair Francis, 2020/11/03
- [PULL v2 07/19] target/riscv: Add V extension state description, Alistair Francis, 2020/11/03
- [PULL v2 04/19] target/riscv: Add basic vmstate description of CPU, Alistair Francis, 2020/11/03
- [PULL v2 08/19] target/riscv: Add sifive_plic vmstate, Alistair Francis, 2020/11/03
- [PULL v2 09/19] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps, Alistair Francis, 2020/11/03
- [PULL v2 10/19] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support, Alistair Francis, 2020/11/03
- [PULL v2 11/19] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules, Alistair Francis, 2020/11/03
- [PULL v2 12/19] hw/misc: Add Microchip PolarFire SoC IOSCB module support, Alistair Francis, 2020/11/03
- [PULL v2 13/19] hw/riscv: microchip_pfsoc: Connect the IOSCB module,
Alistair Francis <=
- [PULL v2 14/19] hw/misc: Add Microchip PolarFire SoC SYSREG module support, Alistair Francis, 2020/11/03
- [PULL v2 15/19] hw/riscv: microchip_pfsoc: Connect the SYSREG module, Alistair Francis, 2020/11/03
- [PULL v2 16/19] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0, Alistair Francis, 2020/11/03
- [PULL v2 17/19] hw/riscv: microchip_pfsoc: Correct DDR memory map, Alistair Francis, 2020/11/03
- [PULL v2 18/19] hw/riscv: microchip_pfsoc: Hook the I2C1 controller, Alistair Francis, 2020/11/03
- [PULL v2 19/19] target/riscv/csr.c : add space before the open parenthesis '(', Alistair Francis, 2020/11/03
- Re: [PULL v2 00/19] riscv-to-apply queue, Peter Maydell, 2020/11/03