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[PULL v2 06/19] target/riscv: Add H extension state description
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From: |
Alistair Francis |
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Subject: |
[PULL v2 06/19] target/riscv: Add H extension state description |
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Date: |
Tue, 3 Nov 2020 07:21:37 -0800 |
From: Yifei Jiang <jiangyifei@huawei.com>
In the case of supporting H extension, add H extension description
to vmstate_riscv_cpu.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-5-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/machine.c | 47 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index fc1461d88e..ae60050898 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -68,6 +68,52 @@ static const VMStateDescription vmstate_pmp = {
}
};
+static bool hyper_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ return riscv_has_ext(env, RVH);
+}
+
+static const VMStateDescription vmstate_hyper = {
+ .name = "cpu/hyper",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = hyper_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(env.hstatus, RISCVCPU),
+ VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
+ VMSTATE_UINTTL(env.hideleg, RISCVCPU),
+ VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
+ VMSTATE_UINTTL(env.htval, RISCVCPU),
+ VMSTATE_UINTTL(env.htinst, RISCVCPU),
+ VMSTATE_UINTTL(env.hgatp, RISCVCPU),
+ VMSTATE_UINT64(env.htimedelta, RISCVCPU),
+
+ VMSTATE_UINT64(env.vsstatus, RISCVCPU),
+ VMSTATE_UINTTL(env.vstvec, RISCVCPU),
+ VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
+ VMSTATE_UINTTL(env.vsepc, RISCVCPU),
+ VMSTATE_UINTTL(env.vscause, RISCVCPU),
+ VMSTATE_UINTTL(env.vstval, RISCVCPU),
+ VMSTATE_UINTTL(env.vsatp, RISCVCPU),
+
+ VMSTATE_UINTTL(env.mtval2, RISCVCPU),
+ VMSTATE_UINTTL(env.mtinst, RISCVCPU),
+
+ VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
+ VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
+ VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
+ VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
+ VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
+ VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
+ VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),
+
+ VMSTATE_END_OF_LIST()
+ }
+};
+
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 1,
@@ -119,6 +165,7 @@ const VMStateDescription vmstate_riscv_cpu = {
},
.subsections = (const VMStateDescription * []) {
&vmstate_pmp,
+ &vmstate_hyper,
NULL
}
};
--
2.28.0
- [PULL v2 00/19] riscv-to-apply queue, Alistair Francis, 2020/11/03
- [PULL v2 02/19] hw/riscv: virt: Allow passing custom DTB, Alistair Francis, 2020/11/03
- [PULL v2 01/19] hw/riscv: sifive_u: Allow passing custom DTB, Alistair Francis, 2020/11/03
- [PULL v2 03/19] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit, Alistair Francis, 2020/11/03
- [PULL v2 05/19] target/riscv: Add PMP state description, Alistair Francis, 2020/11/03
- [PULL v2 06/19] target/riscv: Add H extension state description,
Alistair Francis <=
- [PULL v2 07/19] target/riscv: Add V extension state description, Alistair Francis, 2020/11/03
- [PULL v2 04/19] target/riscv: Add basic vmstate description of CPU, Alistair Francis, 2020/11/03
- [PULL v2 08/19] target/riscv: Add sifive_plic vmstate, Alistair Francis, 2020/11/03
- [PULL v2 09/19] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps, Alistair Francis, 2020/11/03
- [PULL v2 10/19] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support, Alistair Francis, 2020/11/03
- [PULL v2 11/19] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules, Alistair Francis, 2020/11/03
- [PULL v2 12/19] hw/misc: Add Microchip PolarFire SoC IOSCB module support, Alistair Francis, 2020/11/03
- [PULL v2 13/19] hw/riscv: microchip_pfsoc: Connect the IOSCB module, Alistair Francis, 2020/11/03
- [PULL v2 14/19] hw/misc: Add Microchip PolarFire SoC SYSREG module support, Alistair Francis, 2020/11/03
- [PULL v2 15/19] hw/riscv: microchip_pfsoc: Connect the SYSREG module, Alistair Francis, 2020/11/03