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[PULL 11/18] hw/riscv: microchip_pfsoc: Connect DDR memory controller mo
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From: |
Alistair Francis |
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Subject: |
[PULL 11/18] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules |
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Date: |
Thu, 29 Oct 2020 07:13:51 -0700 |
From: Bin Meng <bin.meng@windriver.com>
Connect DDR SGMII PHY module and CFG module to the PolarFire SoC.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-4-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/microchip_pfsoc.h | 5 +++++
hw/riscv/microchip_pfsoc.c | 18 ++++++++++++++++++
hw/riscv/Kconfig | 1 +
3 files changed, 24 insertions(+)
diff --git a/include/hw/riscv/microchip_pfsoc.h
b/include/hw/riscv/microchip_pfsoc.h
index 8bfc7e1a85..5b81e26241 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -24,6 +24,7 @@
#include "hw/char/mchp_pfsoc_mmuart.h"
#include "hw/dma/sifive_pdma.h"
+#include "hw/misc/mchp_pfsoc_dmc.h"
#include "hw/net/cadence_gem.h"
#include "hw/sd/cadence_sdhci.h"
@@ -37,6 +38,8 @@ typedef struct MicrochipPFSoCState {
RISCVHartArrayState e_cpus;
RISCVHartArrayState u_cpus;
DeviceState *plic;
+ MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy;
+ MchpPfSoCDdrCfgState ddr_cfg;
MchpPfSoCMMUartState *serial0;
MchpPfSoCMMUartState *serial1;
MchpPfSoCMMUartState *serial2;
@@ -82,7 +85,9 @@ enum {
MICROCHIP_PFSOC_MMUART0,
MICROCHIP_PFSOC_SYSREG,
MICROCHIP_PFSOC_MPUCFG,
+ MICROCHIP_PFSOC_DDR_SGMII_PHY,
MICROCHIP_PFSOC_EMMC_SD,
+ MICROCHIP_PFSOC_DDR_CFG,
MICROCHIP_PFSOC_MMUART1,
MICROCHIP_PFSOC_MMUART2,
MICROCHIP_PFSOC_MMUART3,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 6aac8497fc..3c504f7c03 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -15,6 +15,7 @@
* 4) Cadence eMMC/SDHC controller and an SD card connected to it
* 5) SiFive Platform DMA (Direct Memory Access Controller)
* 6) GEM (Gigabit Ethernet MAC Controller)
+ * 7) DMC (DDR Memory Controller)
*
* This board currently generates devicetree dynamically that indicates at
least
* two harts and up to five harts.
@@ -103,7 +104,9 @@ static const struct MemmapEntry {
[MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
[MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
[MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
+ [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 },
[MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
+ [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 },
[MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 },
[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
@@ -149,6 +152,11 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
object_initialize_child(obj, "dma-controller", &s->dma,
TYPE_SIFIVE_PDMA);
+ object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy,
+ TYPE_MCHP_PFSOC_DDR_SGMII_PHY);
+ object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg,
+ TYPE_MCHP_PFSOC_DDR_CFG);
+
object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM);
object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM);
@@ -278,6 +286,16 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev,
Error **errp)
memmap[MICROCHIP_PFSOC_MPUCFG].base,
memmap[MICROCHIP_PFSOC_MPUCFG].size);
+ /* DDR SGMII PHY */
+ sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0,
+ memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base);
+
+ /* DDR CFG */
+ sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0,
+ memmap[MICROCHIP_PFSOC_DDR_CFG].base);
+
/* SDHCI */
sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 2df978fe8d..c8e50bde99 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -4,6 +4,7 @@ config IBEX
config MICROCHIP_PFSOC
bool
select CADENCE_SDHCI
+ select MCHP_PFSOC_DMC
select MCHP_PFSOC_MMUART
select MSI_NONBROKEN
select SIFIVE_CLINT
--
2.28.0
- [PULL 03/18] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit, (continued)
- [PULL 03/18] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit, Alistair Francis, 2020/10/29
- [PULL 01/18] hw/riscv: sifive_u: Allow passing custom DTB, Alistair Francis, 2020/10/29
- [PULL 05/18] target/riscv: Add PMP state description, Alistair Francis, 2020/10/29
- [PULL 06/18] target/riscv: Add H extension state description, Alistair Francis, 2020/10/29
- [PULL 04/18] target/riscv: Add basic vmstate description of CPU, Alistair Francis, 2020/10/29
- [PULL 07/18] target/riscv: Add V extension state description, Alistair Francis, 2020/10/29
- [PULL 08/18] target/riscv: Add sifive_plic vmstate, Alistair Francis, 2020/10/29
- [PULL 09/18] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps, Alistair Francis, 2020/10/29
- [PULL 10/18] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support, Alistair Francis, 2020/10/29
- [PULL 12/18] hw/misc: Add Microchip PolarFire SoC IOSCB module support, Alistair Francis, 2020/10/29
- [PULL 11/18] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules,
Alistair Francis <=
- [PULL 13/18] hw/riscv: microchip_pfsoc: Connect the IOSCB module, Alistair Francis, 2020/10/29
- [PULL 15/18] hw/riscv: microchip_pfsoc: Connect the SYSREG module, Alistair Francis, 2020/10/29
- [PULL 14/18] hw/misc: Add Microchip PolarFire SoC SYSREG module support, Alistair Francis, 2020/10/29
- [PULL 16/18] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0, Alistair Francis, 2020/10/29
- [PULL 17/18] hw/riscv: microchip_pfsoc: Correct DDR memory map, Alistair Francis, 2020/10/29
- [PULL 18/18] hw/riscv: microchip_pfsoc: Hook the I2C1 controller, Alistair Francis, 2020/10/29