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[PULL 09/18] hw/riscv: microchip_pfsoc: Document where to look at the So
From: |
Alistair Francis |
Subject: |
[PULL 09/18] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps |
Date: |
Thu, 29 Oct 2020 07:13:49 -0700 |
From: Bin Meng <bin.meng@windriver.com>
It is not easy to find out the memory map for a specific component
in the PolarFire SoC as the information is scattered in different
documents. Add some comments so that people can know where to get
such information from the Microchip website.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-2-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/microchip_pfsoc.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 4627179cd3..6aac8497fc 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -66,6 +66,24 @@
/* GEM version */
#define GEM_REVISION 0x0107010c
+/*
+ * The complete description of the whole PolarFire SoC memory map is scattered
+ * in different documents. There are several places to look at for memory maps:
+ *
+ * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA
+ * Microprocessor Subsystem (MSS) User Guide", which can be downloaded from
+ * https://www.microsemi.com/document-portal/doc_download/
+ * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide,
+ * describes the whole picture of the PolarFire SoC memory map.
+ *
+ * 2 A zip file for PolarFire soC memory map, which can be downloaded from
+ * https://www.microsemi.com/document-portal/doc_download/
+ * 1244581-polarfire-soc-register-map, contains the following 2 major parts:
+ * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm
+ * describes the complete integrated peripherals memory map
+ * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm
+ * describes the complete IOSCB modules memory maps
+ */
static const struct MemmapEntry {
hwaddr base;
hwaddr size;
--
2.28.0
- [PULL 00/18] riscv-to-apply queue, Alistair Francis, 2020/10/29
- [PULL 02/18] hw/riscv: virt: Allow passing custom DTB, Alistair Francis, 2020/10/29
- [PULL 03/18] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit, Alistair Francis, 2020/10/29
- [PULL 01/18] hw/riscv: sifive_u: Allow passing custom DTB, Alistair Francis, 2020/10/29
- [PULL 05/18] target/riscv: Add PMP state description, Alistair Francis, 2020/10/29
- [PULL 06/18] target/riscv: Add H extension state description, Alistair Francis, 2020/10/29
- [PULL 04/18] target/riscv: Add basic vmstate description of CPU, Alistair Francis, 2020/10/29
- [PULL 07/18] target/riscv: Add V extension state description, Alistair Francis, 2020/10/29
- [PULL 08/18] target/riscv: Add sifive_plic vmstate, Alistair Francis, 2020/10/29
- [PULL 09/18] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps,
Alistair Francis <=
- [PULL 10/18] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support, Alistair Francis, 2020/10/29
- [PULL 12/18] hw/misc: Add Microchip PolarFire SoC IOSCB module support, Alistair Francis, 2020/10/29
- [PULL 11/18] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules, Alistair Francis, 2020/10/29
- [PULL 13/18] hw/riscv: microchip_pfsoc: Connect the IOSCB module, Alistair Francis, 2020/10/29
- [PULL 15/18] hw/riscv: microchip_pfsoc: Connect the SYSREG module, Alistair Francis, 2020/10/29
- [PULL 14/18] hw/misc: Add Microchip PolarFire SoC SYSREG module support, Alistair Francis, 2020/10/29
- [PULL 16/18] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0, Alistair Francis, 2020/10/29
- [PULL 17/18] hw/riscv: microchip_pfsoc: Correct DDR memory map, Alistair Francis, 2020/10/29
- [PULL 18/18] hw/riscv: microchip_pfsoc: Hook the I2C1 controller, Alistair Francis, 2020/10/29